17690270. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Moonyong Jang of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17690270 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
Simplified Explanation
The patent application describes a semiconductor package that includes a package substrate, a semiconductor chip, connection pins, and a molding member. Here are the key points:
- The package substrate has wiring patterns in insulation layers and insertion holes that expose portions of the wiring patterns.
- The semiconductor chip is placed on the package substrate and has chip pads on its first surface.
- Connection pins are provided on the chip pads and extend through the insertion holes to connect with the exposed wiring patterns.
- A molding member is placed on the package substrate to cover the semiconductor chip.
Potential applications of this technology:
- Semiconductor packaging for various electronic devices such as smartphones, tablets, and computers.
- Integrated circuits used in automotive electronics, medical devices, and industrial equipment.
Problems solved by this technology:
- Provides a reliable and efficient method for connecting a semiconductor chip to a package substrate.
- Ensures proper electrical connections between the chip pads and the wiring patterns.
- Protects the semiconductor chip from external elements and physical damage.
Benefits of this technology:
- Improved reliability and performance of semiconductor packages.
- Enhanced electrical connectivity between the chip and the package substrate.
- Increased protection for the semiconductor chip, leading to longer lifespan and durability.
Original Abstract Submitted
A semiconductor package includes a package substrate, a semiconductor chip, connection pins and a molding member. The package substrate includes wiring patterns provided respectively in insulation layers, and has insertion holes extending from an upper surface of the package substrate in a thickness direction that expose portions of the wiring patterns in different insulation layers. The semiconductor chip is disposed on the package substrate, and has a first surface on which chip pads are formed. The connection pins are provided on the chip pads, respectively, and extend through corresponding ones of the insertion holes and electrically connect to the portions of the wiring patterns, respectively, that are exposed by the insertion holes. The molding member is provided on the package substrate to cover the semiconductor chip.
