17690058. System and Method for Fabricating a Semiconductor Device simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
System and Method for Fabricating a Semiconductor Device
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Yung-Shun Chen of Taoyuan (TW)
Chih-Chiang Chang of Taipei (TW)
System and Method for Fabricating a Semiconductor Device - A simplified explanation of the abstract
This abstract first appeared for US patent application 17690058 titled 'System and Method for Fabricating a Semiconductor Device
Simplified Explanation
The patent application describes a system for fabricating a semiconductor device using data processors and computer instructions. The system performs various operations, including receiving a layout, extracting parasitic values, generating a modified netlist, performing a post-layout simulation, and fabricating the device.
- The system receives a layout consisting of multiple elements.
- Parasitic values associated with the layout are extracted to create a resistance and capacitance (RC) netlist.
- A modified RC netlist is generated by adding the element names to the RC netlist.
- A post-layout simulation is performed on the modified RC netlist to determine if the layout meets a predetermined specification.
- If the layout meets the specification, a semiconductor device is fabricated based on the layout.
Potential Applications
- Semiconductor manufacturing industry
- Integrated circuit design and fabrication
Problems Solved
- Ensures that a layout meets predetermined specifications before fabrication
- Provides a more accurate representation of the layout by incorporating parasitic values
- Streamlines the fabrication process by automating layout analysis and simulation
Benefits
- Reduces the risk of manufacturing defects by verifying layout specifications
- Improves the efficiency of semiconductor device fabrication
- Enhances the accuracy of post-layout simulations by including parasitic values
Original Abstract Submitted
A system for fabricating a semiconductor device includes one or more data processors configured to perform operations commanded by instructions stored in a non-transitory computer-readable medium. The instructions include receiving a layout including a plurality of elements, extracting parasitic values associated with the layout to generate a resistance and capacitance (RC) netlist, generating a modified RC netlist by adding element names of the elements of the layout to the RC netlist, performing a post-layout simulation on the modified RC netlist to determine whether the layout meets a predetermined specification, and fabricating a semiconductor device based on the layout when it is determined that the layout meets the predetermined specification. The RC netlist includes the extracted parasitic values. The modified RC netlist includes a netlist table storing the element names and the extracted parasitic values.
