17680877. SEMICONDUCTOR PACKAGE INCLUDING STACKED CHIP STRUCTURE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE INCLUDING STACKED CHIP STRUCTURE
Organization Name
Inventor(s)
HYUNGGYUN Noh of SUWON-SI (KR)
JINSOO Bae of SEONGNAM-SI (KR)
DEOKSEON Choi of HWASEONG-SI (KR)
SEMICONDUCTOR PACKAGE INCLUDING STACKED CHIP STRUCTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17680877 titled 'SEMICONDUCTOR PACKAGE INCLUDING STACKED CHIP STRUCTURE
Simplified Explanation
The abstract describes a semiconductor package that includes a package substrate, a lower semiconductor chip, a bonding wire, an upper semiconductor chip, and a molding portion.
- The package substrate has a bonding pad on its upper surface.
- The lower semiconductor chip is placed on the upper surface of the package substrate.
- The upper surface of the lower semiconductor chip has a connect edge region with a connection pad and an open edge region with a dam structure containing dummy bumps.
- A bonding wire connects the bonding pad and the connection pad, with a specific height above the upper surface of the lower semiconductor chip.
- The upper semiconductor chip is positioned on top of the lower semiconductor chip using an inter-chip bonding layer.
- A molding portion surrounds both the lower and upper semiconductor chips on the package substrate.
Potential applications of this technology:
- Semiconductor packaging for various electronic devices such as smartphones, tablets, and computers.
- Integration of multiple semiconductor chips in a compact package.
Problems solved by this technology:
- Provides a reliable connection between the bonding pad and the connection pad using a bonding wire.
- Ensures proper alignment and bonding of the upper semiconductor chip on top of the lower semiconductor chip.
- Protects the semiconductor chips from external elements and physical damage with the molding portion.
Benefits of this technology:
- Improved performance and functionality of electronic devices through efficient semiconductor packaging.
- Enhanced reliability and durability of the semiconductor package.
- Cost-effective manufacturing process for semiconductor packages.
Original Abstract Submitted
A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.
