17677329. METHODS OF FORMING INTEGRATED CIRCUIT DEVICES INCLUDING STACKED TRANSISTORS AND INTEGRATED CIRCUIT DEVICES FORMED BY THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
METHODS OF FORMING INTEGRATED CIRCUIT DEVICES INCLUDING STACKED TRANSISTORS AND INTEGRATED CIRCUIT DEVICES FORMED BY THE SAME
Organization Name
Inventor(s)
Jaehyun Park of Hwaseong-si (KR)
Mehdi Saremi of Danville CA (US)
Rebecca Park of Mountain View CA (US)
Harsono Simka of Saratoga CA (US)
METHODS OF FORMING INTEGRATED CIRCUIT DEVICES INCLUDING STACKED TRANSISTORS AND INTEGRATED CIRCUIT DEVICES FORMED BY THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17677329 titled 'METHODS OF FORMING INTEGRATED CIRCUIT DEVICES INCLUDING STACKED TRANSISTORS AND INTEGRATED CIRCUIT DEVICES FORMED BY THE SAME
Simplified Explanation
The patent application describes a method for forming an integrated circuit device using a preliminary transistor stack on a substrate. The method involves several steps, including the formation of sacrificial layers, active regions, and source/drain regions, as well as the conversion of a preliminary capping layer into an insulating material.
- The method involves providing a preliminary transistor stack on a substrate.
- The preliminary transistor stack includes sacrificial layers, active regions, and source/drain regions.
- Lower source/drain regions are formed on the lower active region.
- A preliminary capping layer, made of a semiconductor material, is formed on one of the lower source/drain regions.
- The preliminary capping layer is converted into a capping layer made of an insulating material.
- Upper source/drain regions are formed on the upper active region.
Potential applications of this technology:
- Integrated circuit manufacturing
- Semiconductor device fabrication
Problems solved by this technology:
- Provides a method for forming an integrated circuit device with improved performance and reliability.
- Allows for the formation of source/drain regions and capping layers in a more efficient and precise manner.
Benefits of this technology:
- Improved performance and reliability of integrated circuit devices.
- Enhanced efficiency and precision in the formation of source/drain regions and capping layers.
Original Abstract Submitted
Integrated circuit devices and methods of forming the integrated circuit device are provided. The methods may include providing a preliminary transistor stack including an upper sacrificial layer on a substrate, an upper active region between the substrate and the upper sacrificial layer, a lower sacrificial layer between the substrate and the upper active region, and a lower active region between the substrate and the lower sacrificial layer. The methods may further include forming lower source/drain regions on respective opposing side surfaces of the lower active region, forming a preliminary capping layer on a first lower source/drain region of the lower source/drain regions, the preliminary capping layer including a semiconductor material, converting the preliminary capping layer to a capping layer that includes an insulating material, and forming upper source/drain regions on respective opposing side surfaces of the upper active region.
