17674908. SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME simplified abstract (Samsung Electronics Co., Ltd.)
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
Organization Name
Inventor(s)
Hundae Choi of Hwaseong-si (KR)
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17674908 titled 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
Simplified Explanation
The patent application describes a semiconductor memory device that includes a mode register set and a clock correction circuit. The mode register set stores a control code set, while the clock correction circuit corrects phase skews and duty errors of clock signals during a duty training interval.
- The semiconductor memory device includes a mode register set and a clock correction circuit.
- The mode register set stores a first control code set.
- The clock correction circuit divides the duty training interval into three consecutive intervals.
- During the first interval, the circuit corrects the phase skew of the first and third clock signals.
- During the second interval, the circuit corrects the phase skew of the second and fourth clock signals.
- During the third interval, the circuit corrects the phase skew of the first and fourth clock signals.
- The semiconductor memory device enhances the signal integrity of clock signals by correcting duty errors and phase skews during the duty training interval.
Potential Applications
- Semiconductor memory devices
- Integrated circuits
- Computer systems
Problems Solved
- Signal integrity issues in clock signals
- Duty errors and phase skews in clock signals
Benefits
- Enhanced signal integrity of clock signals
- Improved performance and reliability of semiconductor memory devices
- More accurate timing synchronization in computer systems
Original Abstract Submitted
A semiconductor memory device includes a mode register set and a clock correction circuit. The mode register set stores a first control code set. During a duty training interval based on a duty training command, the clock correction circuit may divide the duty training interval into a first interval, a second interval and a third interval which are consecutive, may correct a phase skew of a first clock signal and a third clock signal during the first interval, may correct a phase skew of a second clock signal and a fourth clock signal during the second interval, and may correct a phase skew of the first clock signal and the fourth clock signal during the third interval. The semiconductor memory device may enhance signal integrity of clock signals by correcting duty errors and phase skews of the clock signals having multi-phases during the duty training interval.
