17662316. SEMICONDUCTOR DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
Jonghyuk Park of Hwaseong-si (KR)
Ilyoung Yoon of Hwaseong-si (KR)
SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17662316 titled 'SEMICONDUCTOR DEVICE
Simplified Explanation
The patent application describes a semiconductor device that includes a substrate with different regions, lower electrodes, a dielectric layer, a silicon germanium layer, a metal plate pattern, a polishing stop layer pattern, and upper contact plugs.
- The device has a substrate with a cell region and a peripheral region.
- Lower electrodes are placed on the cell region of the substrate.
- A dielectric layer is applied on the surfaces of the lower electrodes.
- A silicon germanium layer is deposited on top of the dielectric layer.
- A metal plate pattern and a polishing stop layer pattern are stacked on the silicon germanium layer.
- Upper contact plugs physically contact the upper surface of the silicon germanium layer.
- The upper contact plugs are positioned higher than the polishing stop layer pattern.
- The upper contact plugs are spaced apart from the metal plate pattern and the polishing stop layer pattern.
Potential applications of this technology:
- Semiconductor manufacturing
- Electronics industry
- Integrated circuits
Problems solved by this technology:
- Provides a structure for a semiconductor device with improved performance and reliability.
- Enables efficient contact between the upper contact plugs and the silicon germanium layer.
Benefits of this technology:
- Enhanced performance and reliability of semiconductor devices.
- Improved contact between different layers of the device.
- Enables more efficient manufacturing processes.
Original Abstract Submitted
A semiconductor device may include a substrate including a cell region and a peripheral region, lower electrodes on the cell region of the substrate, a dielectric layer on surfaces of the lower electrodes, a silicon germanium layer on the dielectric layer, a metal plate pattern and a polishing stop layer pattern stacked on the silicon germanium layer, and upper contact plugs physically contacting an upper surface of the silicon germanium layer. The upper contact plugs may have an upper surface farther away from the substrate than an upper surface of the polishing stop layer pattern. The upper contact plugs may be spaced apart from the metal plate pattern and the polishing stop layer pattern.
