17648037. Dummy Hybrid Film for Self-Alignment Contact Formation simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
Dummy Hybrid Film for Self-Alignment Contact Formation
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Bor Chiuan Hsieh of Taoyuan City (TW)
Tsai-Jung Ho of Xihu Township (TW)
Dummy Hybrid Film for Self-Alignment Contact Formation - A simplified explanation of the abstract
This abstract first appeared for US patent application 17648037 titled 'Dummy Hybrid Film for Self-Alignment Contact Formation
Simplified Explanation
The patent application describes a method for forming a source/drain contact opening in a semiconductor device. Here are the key points:
- A dummy gate stack is formed over a semiconductor region.
- Gate spacers are formed on both sides of the dummy gate stack.
- A source/drain region is formed on one side of the dummy gate stack.
- An inter-layer dielectric is formed over the source/drain region.
- The dummy gate stack is replaced with a replacement gate stack.
- The replacement gate stack is recessed to create a recess between the gate spacers.
- A liner is deposited into the recess.
- A masking layer is deposited over the liner and extends into the recess.
- An etching mask is formed to cover a portion of the masking layer.
- The inter-layer dielectric is etched to create a source/drain contact opening.
- A source/drain contact plug is formed in the source/drain contact opening.
- A gate contact plug is formed between the gate spacers, connecting to the replacement gate stack.
Potential applications of this technology:
- Semiconductor device manufacturing
- Integrated circuit fabrication
Problems solved by this technology:
- Efficient formation of a source/drain contact opening
- Improved connectivity between the replacement gate stack and gate contact plug
Benefits of this technology:
- Enhanced performance and functionality of semiconductor devices
- Increased reliability and efficiency in integrated circuits.
Original Abstract Submitted
A method includes forming a dummy gate stack over a semiconductor region, forming gate spacers on opposing sides of the dummy gate stack, forming a source/drain region on a side of the dummy gate stack, forming an inter-layer dielectric over the source/drain region, replacing the dummy gate stack with a replacement gate stack, recessing the replacement gate stack to form a recess between the gate spacers, depositing a liner extending into the recess, depositing a masking layer over the liner and extending into the recess, forming an etching mask covering a portion of the masking layer, and etching the inter-layer dielectric to form a source/drain contact opening. The source/drain region is underlying and exposed to the source/drain contact opening. A source/drain contact plug is formed in the source/drain contact opening. A gate contact plug extends between the gate spacers and electrically connecting to the replacement gate stack.
