17644528. CROSS BAR VERTICAL FETS simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)
Contents
CROSS BAR VERTICAL FETS
Organization Name
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor(s)
Brent A. Anderson of Jericho VT (US)
Junli Wang of Slingerlands NY (US)
Indira Seshadri of Niskayuna NY (US)
Ruilong Xie of Niskayuna NY (US)
Dechao Guo of Niskayuna NY (US)
CROSS BAR VERTICAL FETS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17644528 titled 'CROSS BAR VERTICAL FETS
Simplified Explanation
The abstract describes a patent application for a crossbar VFET (Vertical Field Effect Transistor) with reduced or no corner rounding in the channel structure. This is achieved by using a masking feature before etching the channels, resulting in improved channel structure.
- The patent application is for a crossbar VFET with reduced or no corner rounding in the channel structure.
- The channel (or fin) that extends between a pair of channels (fins) is the focus of the innovation.
- A masking feature is developed before etching the channels in the VFET.
- The masking feature helps to achieve reduced or no corner rounding in the channel structure.
- This innovation improves the performance and efficiency of the VFET.
Potential Applications
- Electronics industry
- Semiconductor manufacturing
- Integrated circuits
- Transistors
Problems Solved
- Corner rounding in the channel structure of a crossbar VFET
- Reduced performance and efficiency due to corner rounding
- Manufacturing challenges in achieving precise channel structures
Benefits
- Improved performance and efficiency of the VFET
- Enhanced functionality of the crossbar VFET
- More precise and controlled channel structures
- Increased reliability and lifespan of the VFET
Original Abstract Submitted
The embodiments herein describe a crossbar VFET where the crossbar channel (or fin) that extends between a pair of channels (fins) has reduced corner rounding, or no corner rounding. This can be achieved by developing a masking feature before etching the channels in the VFET that results in reduced, or no corner rounding in the channel structure etched using the masking feature.
