17644463. SIDEWALL EPITAXY ENCAPSULATION FOR NANOSHEET I/O DEVICE simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)
SIDEWALL EPITAXY ENCAPSULATION FOR NANOSHEET I/O DEVICE
Organization Name
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor(s)
Ruqiang Bao of Niskayuna NY (US)
Shogo Mochizuki of Mechanicville NY (US)
SIDEWALL EPITAXY ENCAPSULATION FOR NANOSHEET I/O DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17644463 titled 'SIDEWALL EPITAXY ENCAPSULATION FOR NANOSHEET I/O DEVICE
Simplified Explanation
The patent application describes a semiconductor structure that includes two nanosheet fins extending vertically from different regions of a substrate. One nanosheet fin is for a logic device, and the other is for an input/output device. The first nanosheet fin has semiconductor channel layers stacked over the substrate region, while the second nanosheet fin has alternating sacrificial and semiconductor channel layers. An encapsulation layer is grown only along the sidewalls of the second nanosheet fin.
- The semiconductor structure includes two nanosheet fins for different types of devices.
- The first nanosheet fin has semiconductor channel layers stacked over the substrate region.
- The second nanosheet fin has alternating sacrificial and semiconductor channel layers.
- An encapsulation layer is grown only along the sidewalls of the second nanosheet fin.
Potential Applications
This technology can be applied in various semiconductor devices, such as:
- Logic devices
- Input/output devices
Problems Solved
The semiconductor structure addresses the following problems:
- Integration of different types of devices on a single substrate
- Efficient use of space in semiconductor devices
Benefits
The benefits of this technology include:
- Improved integration of logic and input/output devices
- Enhanced performance and functionality of semiconductor devices
- Space-saving design for more compact devices.
Original Abstract Submitted
A semiconductor structure includes a first nanosheet fin extending vertically from a first region of a substrate corresponding to a logic device and a second nanosheet fin extending vertically from a second region of the substrate corresponding to an input/output device. The first nanosheet fin includes first semiconductor channel layers vertically stacked over the first region of the substrate, while the second nanosheet fin includes an alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers. The semiconductor structure further includes an epitaxially grown encapsulation layer disposed only along sidewalls of the second nanosheet fin.
