17644100. SELECTIVE GATE CAP FOR SELF-ALIGNED CONTACTS simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

SELECTIVE GATE CAP FOR SELF-ALIGNED CONTACTS

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Ruilong Xie of Niskayuna NY (US)

CHANRO Park of CLIFTON PARK NY (US)

Julien Frougier of Albany NY (US)

Kangguo Cheng of Schenectady NY (US)

Eric Miller of Watervliet NY (US)

Ekmini Anuja De Silva of Slingerlands NY (US)

SELECTIVE GATE CAP FOR SELF-ALIGNED CONTACTS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17644100 titled 'SELECTIVE GATE CAP FOR SELF-ALIGNED CONTACTS

Simplified Explanation

The abstract describes a semiconductor device that includes a self-aligned contact gate dielectric cap, or "SAC cap," which is located over the gate stack and spacer. The SAC cap has an ear that extends over the sidewall of the spacer where no source/drain (S/D) contact is formed. The method of forming this semiconductor device involves several steps, including forming the gate stack, recessing the interlayer dielectric (ILD) to create topography, depositing a selective gate cap over the gate stack, and forming a self-aligned contact with respect to the selective gate cap.

• The semiconductor device includes a self-aligned contact gate dielectric cap (SAC cap) over the gate stack and spacer.
• The SAC cap has an ear that extends over the sidewall of the spacer where no S/D contact is formed.
• The method of forming the semiconductor device involves steps such as forming the gate stack, recessing the ILD, depositing a selective gate cap, and forming a self-aligned contact.

Potential applications of this technology:

• Semiconductor manufacturing industry
• Integrated circuit fabrication
• Electronic devices and components

Problems solved by this technology:

• Provides a self-aligned contact gate dielectric cap that improves the performance and reliability of semiconductor devices.
• Helps to prevent leakage and short-circuits in the device.
• Enhances the overall efficiency and functionality of the semiconductor device.

Benefits of this technology:

• Improved performance and reliability of semiconductor devices.
• Enhanced efficiency and functionality.
• Reduced risk of leakage and short-circuits.
• Simplified manufacturing process.

Original Abstract Submitted

A semiconductor device having a self-aligned contact gate dielectric cap, or “SAC cap” over the gate stack and spacer. A SAC cap ear exists over the sidewall of a top portion of the spacer at a location where no S/D contact is formed. A method of forming the semiconductor device comprises: (i) forming gate stack; (ii) recessing ILD to create topography of the gate stack; (iii) forming selective gate cap deposition over the gate stack; and/or (iv) forming self-aligned contact with respect to the selective gate cap.