17644076. METAL GATE PATTERNING FOR LOGIC AND SRAM IN NANOSHEET DEVICES simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

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METAL GATE PATTERNING FOR LOGIC AND SRAM IN NANOSHEET DEVICES

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

CHOONGHYUN Lee of CHIGASAKI (JP)

TAKASHI Ando of EASTCHESTER NY (US)

JINGYUN Zhang of ALBANY NY (US)

ALEXANDER Reznicek of TROY NY (US)

METAL GATE PATTERNING FOR LOGIC AND SRAM IN NANOSHEET DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17644076 titled 'METAL GATE PATTERNING FOR LOGIC AND SRAM IN NANOSHEET DEVICES

Simplified Explanation

The abstract describes a semiconductor device that includes two nanosheet stacks formed on a substrate, with alternating layers of a work function metal (WFM) gate layer and an active semiconductor layer. A shallow trench isolation (STI) region is formed between the nanosheet stacks, and an STI divot is formed within the STI region. The first WFM gate layer of the first nanosheet stack is formed within the STI divot.

  • The semiconductor device includes two nanosheet stacks with alternating layers of a WFM gate layer and an active semiconductor layer.
  • A shallow trench isolation (STI) region is formed between the nanosheet stacks.
  • An STI divot is formed within the STI region.
  • The first WFM gate layer of the first nanosheet stack is formed within the STI divot.

Potential Applications

  • This semiconductor device can be used in various electronic devices such as smartphones, tablets, and computers.
  • It can be utilized in the development of advanced integrated circuits and microprocessors.

Problems Solved

  • The semiconductor device solves the problem of efficiently integrating multiple nanosheet stacks on a substrate.
  • The STI divot helps in optimizing the performance and functionality of the device.

Benefits

  • The use of nanosheet stacks improves the performance and power efficiency of the semiconductor device.
  • The STI divot allows for better control and manipulation of the WFM gate layer, enhancing the overall functionality of the device.
  • The device enables the development of smaller and more compact electronic devices without compromising performance.


Original Abstract Submitted

A semiconductor device is provided. The semiconductor device includes a first device including a first nanosheet stack formed on a substrate, the first nanosheet stack including alternating layers of a first work function metal (WFM) gate layer and an active semiconductor layer, a second nanosheet stack formed on the substrate, the second nanosheet stack including alternating layers of a second WFM gate layer and the active semiconductor layer, a shallow trench isolation (STI) region formed in the substrate between the first nanosheet stack and the second nanosheet stack, and an STI divot formed in the STI region. The first WFM gate layer of the first nanosheet stack is formed in the STI divot.

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