17643408. ACCURATE METAL LINE AND VIA HEIGHT CONTROL FOR TOP VIA PROCESS simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

ACCURATE METAL LINE AND VIA HEIGHT CONTROL FOR TOP VIA PROCESS

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

TSUNG-SHENG Kang of Ballston Lake NY (US)

RUILONG Xie of Niskayuna NY (US)

TAO Li of Slingerlands NY (US)

CHIH-CHAO Yang of Glenmont NY (US)

ACCURATE METAL LINE AND VIA HEIGHT CONTROL FOR TOP VIA PROCESS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17643408 titled 'ACCURATE METAL LINE AND VIA HEIGHT CONTROL FOR TOP VIA PROCESS

Simplified Explanation

The abstract describes a method for manufacturing an interconnect structure for a semiconductor device. Here is a simplified explanation of the patent application:

• The method starts by forming a metal interconnect layer on a substrate.
• A hardmask is then formed on top of the metal interconnect layer.
• The metal interconnect layer and hardmask are patterned to create the desired interconnect structure.
• A sacrificial material layer is applied to overfill the patterned interconnect layer and hardmask.
• A portion of the sacrificial layer and hardmask is selectively removed to create a via opening.
• Finally, a via is formed on the metal interconnect layer within the via opening using a selective metal growth process.

Potential applications of this technology:

• Manufacturing interconnect structures for semiconductor devices.
• Improving the performance and functionality of integrated circuits.

Problems solved by this technology:

• Provides a method for creating precise and reliable interconnect structures in semiconductor devices.
• Enables the formation of vias with high aspect ratios, allowing for more efficient use of space on the semiconductor device.

Benefits of this technology:

• Allows for the creation of complex interconnect structures with improved electrical conductivity.
• Enhances the overall performance and reliability of semiconductor devices.
• Enables the integration of more advanced features and functionalities in integrated circuits.

Original Abstract Submitted

A method of manufacturing an interconnect structure for a semiconductor device is provided. The method includes forming a metal interconnect layer on a substrate. The method includes forming a hardmask on the metal interconnect layer, patterning the metal interconnect layer and hardmask, forming a sacrificial material layer to overfill the patterned metal interconnect layer and hardmask, and selectively removing a portion of the sacrificial layer and the hardmask to form a via opening. The method also includes forming a via on the metal interconnect layer in the via opening by a selective metal growth process.