17643362. STACKED FIELD EFFECT TRANSISTORS simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

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STACKED FIELD EFFECT TRANSISTORS

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Sung Dae Suk of Watervliet NY (US)

Timothy Mathew Philip of Albany NY (US)

Junli Wang of Slingerlands NY (US)

Dechao Guo of Niskayuna NY (US)

Chen Zhang of Guilderland NY (US)

STACKED FIELD EFFECT TRANSISTORS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17643362 titled 'STACKED FIELD EFFECT TRANSISTORS

Simplified Explanation

The abstract describes a patent application for stacked field effect transistors. These transistors have a first power rail, a second power rail, a first Field Effect Transistor (FET) connected to the first power rail, a second FET connected to the second power rail, and an insulator separating the two FETs. The first power rail, second power rail, first FET, and second FET are aligned on a shared axis, with the power rails located on opposite sides of the device.

  • Stacked field effect transistors with aligned power rails and FETs
  • First FET connected to first power rail, second FET connected to second power rail
  • Insulator separates the two FETs
  • Power rails located on opposite sides of the device

Potential Applications

  • Integrated circuits
  • Electronics manufacturing
  • Power management systems

Problems Solved

  • Improved alignment and organization of power rails and FETs
  • Enhanced performance and efficiency of stacked transistors
  • Simplified manufacturing process

Benefits

  • Increased functionality and performance of integrated circuits
  • Improved power management and energy efficiency
  • Streamlined manufacturing process


Original Abstract Submitted

Stacked field effect transistors are provided such having a first power rail; a second power rail; a first Field Effect Transistor (FET) having a first gate connected to the first power rail; a second FET having a second gate connected to the second power rail; and an insulator separating the first FET from the second FET, wherein the first power rail, the second power rail, the first FET, and the second FET are aligned on a shared axis, and wherein the first power rail and the second power rail are located on opposite sides of the device.