17637893. DUAL GATE ARRAY SUBSTRATE AND DISPLAY PANEL simplified abstract (BOE TECHNOLOGY GROUP CO., LTD.)
Contents
- 1 DUAL GATE ARRAY SUBSTRATE AND DISPLAY PANEL
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DUAL GATE ARRAY SUBSTRATE AND DISPLAY PANEL - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
DUAL GATE ARRAY SUBSTRATE AND DISPLAY PANEL
Organization Name
BOE TECHNOLOGY GROUP CO., LTD.
Inventor(s)
Dongchuan Chen of Beijing (CN)
DUAL GATE ARRAY SUBSTRATE AND DISPLAY PANEL - A simplified explanation of the abstract
This abstract first appeared for US patent application 17637893 titled 'DUAL GATE ARRAY SUBSTRATE AND DISPLAY PANEL
Simplified Explanation
The dual gate array substrate of the present disclosure includes a plurality of groups of dual gate lines, a plurality of data lines, a plurality of pixel pairs, and a plurality of common electrode lines. Each common electrode line is arranged between two pixel units in the same pixel pair and is connected to common electrodes of the two pixel units through two first vias. The layer where the common electrode line is located and the layer where a source/drain electrode of a thin film transistor is located are different layers and insulated from each other. The two first vias are on both sides of the data line.
- The substrate includes multiple groups of dual gate lines, data lines, pixel pairs, and common electrode lines.
- Common electrode lines are positioned between pixel units in the same pair and connected through vias.
- Common electrode and source/drain electrode layers are separate and insulated.
- First vias are located on either side of the data line.
Potential Applications
The technology described in this patent application could be applied in the following areas:
- Display panels
- Touchscreen devices
- Flexible electronics
Problems Solved
This technology addresses the following issues:
- Improved pixel pair connectivity
- Enhanced insulation between electrode layers
- Efficient data line routing
Benefits
The benefits of this technology include:
- Higher display resolution
- Increased durability of electronic devices
- Enhanced performance of thin film transistors
Potential Commercial Applications
The potential commercial applications of this technology could be seen in:
- Consumer electronics
- Medical devices
- Automotive displays
Possible Prior Art
One possible prior art for this technology could be the use of single gate arrays in display panels and electronic devices.
Unanswered Questions
How does this technology compare to existing dual gate array substrates in terms of performance and cost?
This article does not provide a direct comparison with existing dual gate array substrates in terms of performance and cost.
Are there any limitations or drawbacks to implementing this technology in current electronic devices?
The article does not mention any limitations or drawbacks to implementing this technology in current electronic devices.
Original Abstract Submitted
The dual gate array substrate of the present disclosure includes a plurality of groups of dual gate lines, a plurality of data lines, a plurality of pixel pairs and a plurality of common electrode lines, each common electrode line is arranged between two pixel units in a same pixel pair and is connected to common electrodes of the two pixel units through two first vias; a layer where the common electrode line is located and a layer where a source/drain electrode of a thin film transistor is located are different layers and insulated from each other; the two first vias are on both sides of the data line.
