17592629. SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Organization Name
Inventor(s)
Sun Young Noh of Hwaseong-si (KR)
Wan Don Kim of Seongnam-si (KR)
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17592629 titled 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Simplified Explanation
The patent application describes a semiconductor device that includes multiple layers of interlayer insulating layers and wiring patterns. It also includes a via trench and a via that connects the wiring patterns.
- The semiconductor device has a substrate and multiple layers of interlayer insulating layers.
- Each interlayer insulating layer has a wiring pattern in a trench.
- The wiring patterns are separated by the interlayer insulating layers.
- The device also includes a via trench that extends from one wiring pattern to another.
- The via is made up of a via barrier layer and a via filling layer.
- The via connects the wiring patterns together.
Potential applications of this technology:
- Integrated circuits
- Microprocessors
- Memory devices
Problems solved by this technology:
- Efficiently connecting multiple wiring patterns in a semiconductor device
- Reducing signal delay and power consumption in the device
Benefits of this technology:
- Improved performance and functionality of semiconductor devices
- Enhanced reliability and durability
- Increased integration density
Original Abstract Submitted
A semiconductor device includes: a substrate; a first interlayer insulating layer on the substrate; a first wiring pattern in a first trench of the first interlayer insulating layer; a second interlayer insulating layer on the first interlayer insulating layer; a second wiring pattern in a second trench of the second interlayer insulating layer; a third interlayer insulating layer on the second interlayer insulating layer; a third wiring pattern in a third trench of the third interlayer insulating layer, and including a wiring barrier layer and a wiring filling layer, wherein the wiring filling layer contacts the third interlayer insulating layer; a via trench extending from the first wiring pattern to the third trench; and a via including a via barrier layer and a via filling layer. The via barrier layer is in the via trench. The via filling layer contacts the first wiring pattern and the wiring filling layer.
