17586767. EFFICIENT AND CONCURRENT MODEL EXECUTION simplified abstract (Samsung Electronics Co., Ltd.)

From WikiPatents
Jump to navigation Jump to search

EFFICIENT AND CONCURRENT MODEL EXECUTION

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Marie Mai Nguyen of Pittsburgh PA (US)

Rekha Pitchumani of Oak Hill VA (US)

Zongwang Li of Dublin CA (US)

Yang Seok Ki of Palo Alto CA (US)

Krishna Teja Malladi of San Jose CA (US)

EFFICIENT AND CONCURRENT MODEL EXECUTION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17586767 titled 'EFFICIENT AND CONCURRENT MODEL EXECUTION

Simplified Explanation

The patent application describes an accelerator that includes two tiers of storage and a bus for transferring data between them.

  • The accelerator circuit processes data to produce processed data.
  • The first tier storage has a smaller capacity and faster latency compared to the second tier storage.
  • The second tier storage has a larger capacity but slower latency.
  • The bus is used to transfer data or processed data between the two tiers of storage.

Potential applications of this technology:

  • High-performance computing systems
  • Data centers
  • Artificial intelligence and machine learning applications
  • Big data analytics

Problems solved by this technology:

  • Efficient data processing by utilizing two tiers of storage with different capacities and latencies.
  • Reducing the need for frequent data transfers between storage tiers, improving overall system performance.

Benefits of this technology:

  • Improved data processing speed and efficiency.
  • Optimal utilization of storage resources.
  • Enhanced performance in handling large datasets.
  • Cost-effective solution for data-intensive applications.


Original Abstract Submitted

An accelerator is disclosed. A circuit may process a data to produce a processed data. A first tier storage may include a first capacity and a first latency. A second tier storage may include a second capacity and a second latency. The second capacity may be larger than the first capacity, and the second latency may be slower than the first latency. A bus may be used to transfer at least one of the data or the processed data between the first tier storage and the second tier storage.