17586310. SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

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SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Chun-Hung Huang of Hsinchu (TW)

Hsin-Che Chiang of Taipei City (TW)

Jeng-Ya Yeh of New Taipei City (TW)

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 17586310 titled 'SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

Simplified Explanation

The abstract describes a method of forming a semiconductor device structure. Here are the key points:

  • The method involves forming semiconductor fins in different conductivity type regions of a substrate.
  • A sacrificial gate structure is then formed across a portion of the semiconductor fins, consisting of a sacrificial gate dielectric layer and a sacrificial gate electrode layer.
  • The sacrificial gate dielectric layer on the semiconductor fins of one conductivity type region is asymmetrical in thickness between the top and the sidewall of the fins.
  • A gate spacer is formed on the sidewalls of the sacrificial gate structure.
  • The semiconductor fins not covered by the sacrificial gate structure and the gate spacer are recessed.
  • Source/drain features are formed on the recessed semiconductor fins.
  • Finally, the sacrificial gate structure is removed to expose the top of the semiconductor fins.

Potential applications of this technology:

  • This method can be used in the fabrication of semiconductor devices, such as transistors, integrated circuits, and other electronic components.
  • It can be applied in various industries, including electronics, telecommunications, computing, and consumer electronics.

Problems solved by this technology:

  • The method provides a way to form semiconductor fins with an asymmetrical sacrificial gate dielectric layer, which can enhance the performance and functionality of the semiconductor device.
  • It allows for precise control over the thickness of the sacrificial gate dielectric layer, which can improve the electrical characteristics of the device.

Benefits of this technology:

  • The method enables the formation of semiconductor fins with improved performance and functionality.
  • It offers greater flexibility in designing and optimizing the semiconductor device structure.
  • The precise control over the sacrificial gate dielectric layer thickness can lead to enhanced electrical characteristics and overall device performance.


Original Abstract Submitted

A method of forming a semiconductor device structure is provided. The method includes forming semiconductor fins at a first conductivity type region and a second conductivity type region of a substrate, forming a sacrificial gate structure across a portion of the semiconductor fins, wherein the sacrificial gate structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer over the sacrificial gate dielectric layer, and the sacrificial gate dielectric layer on the semiconductor fins of the first conductivity type region is asymmetrical in thickness between a top and a sidewall of the semiconductor fins. The method also includes forming a gate spacer on opposite sidewalls of the sacrificial gate structure, recessing the semiconductor fins not covered by the sacrificial gate structure and the gate spacer, forming source/drain feature on the recessed semiconductor fins, and removing the sacrificial gate structure to expose the top of the semiconductor fins.

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