17581787. INTEGRATED CIRCUIT WITH CONDUCTIVE VIA FORMATION ON SELF-ALIGNED GATE METAL CUT simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
INTEGRATED CIRCUIT WITH CONDUCTIVE VIA FORMATION ON SELF-ALIGNED GATE METAL CUT
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Chia-Hao Chang of Hsinchu (TW)
Kuo-Cheng Chiang of Hsinchu (TW)
INTEGRATED CIRCUIT WITH CONDUCTIVE VIA FORMATION ON SELF-ALIGNED GATE METAL CUT - A simplified explanation of the abstract
This abstract first appeared for US patent application 17581787 titled 'INTEGRATED CIRCUIT WITH CONDUCTIVE VIA FORMATION ON SELF-ALIGNED GATE METAL CUT
Simplified Explanation
The abstract describes an integrated circuit that includes two nanostructure transistors with separate gate electrodes. A dielectric isolation structure separates the gate electrodes, and a gate connection metal is placed on top of both electrodes. The metal is patterned to expose certain areas of the electrodes adjacent to the isolation structure, and a conductive via contacts the exposed area of the second gate electrode.
- The integrated circuit includes two nanostructure transistors with separate gate electrodes.
- A dielectric isolation structure separates the gate electrodes.
- A gate connection metal is placed on top of both gate electrodes.
- The gate connection metal is patterned to expose specific areas of the electrodes adjacent to the isolation structure.
- A conductive via is used to contact the exposed area of the second gate electrode.
Potential Applications
- Integrated circuits for electronic devices
- Nanoelectronics
- Semiconductor industry
Problems Solved
- Improved integration of nanostructure transistors
- Enhanced connectivity between gate electrodes
- Efficient use of space on the integrated circuit
Benefits
- Higher performance and functionality of integrated circuits
- Improved reliability and stability of the circuit
- Increased miniaturization and density of components
Original Abstract Submitted
An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.
