17578428. ACCELERATE NEURAL NETWORKS WITH COMPRESSION AT DIFFERENT LEVELS simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
ACCELERATE NEURAL NETWORKS WITH COMPRESSION AT DIFFERENT LEVELS
Organization Name
Inventor(s)
Ali Shafiee Ardestani of Santa Clara CA (US)
ACCELERATE NEURAL NETWORKS WITH COMPRESSION AT DIFFERENT LEVELS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17578428 titled 'ACCELERATE NEURAL NETWORKS WITH COMPRESSION AT DIFFERENT LEVELS
Simplified Explanation
The abstract describes a neural network accelerator that consists of multiplier circuits, shifter circuits, and an adder tree circuit. The accelerator performs multiplication and addition operations on values represented by a predetermined number of bits.
- The neural network accelerator includes 2 multiplier circuits, 2 shifter circuits, and an adder tree circuit.
- Each multiplier circuit multiplies a first value by a second value to produce a first product value.
- The first value is represented by a predetermined number of bits starting from the most significant bit with a value of 1.
- The second value is represented by a predetermined number of bits.
- The first product value is represented by a predetermined number of bits.
- Each shifter circuit takes the first product value from the corresponding multiplier circuit and left shifts it by the predetermined number of bits to generate a second product value.
- The adder tree circuit adds all the second product values to obtain a partial-sum value represented by a predetermined number of bits.
Potential applications of this technology:
- Accelerating neural network computations in various fields such as image recognition, natural language processing, and autonomous vehicles.
- Improving the performance and efficiency of neural network models in edge devices and embedded systems.
Problems solved by this technology:
- Speeding up the computation of neural networks by offloading the workload to dedicated hardware.
- Reducing power consumption and latency in neural network inference tasks.
Benefits of this technology:
- Faster execution of neural network computations due to dedicated hardware acceleration.
- Improved energy efficiency and reduced power consumption compared to software-based implementations.
- Enables real-time processing of neural network models in resource-constrained devices.
Original Abstract Submitted
A neural network accelerator includes 2 multiplier circuits, 2 shifter circuits and an adder tree circuit. Each respective multiplier circuit multiplies a first value by a second value to output a first product value. Each respective first value is represented by a first predetermined number of bits beginning at a most significant bit of the first value having a value equal to 1. Each respective second value is represented by a second predetermined number of bits, and each respective first product value is represented by a third predetermined number of bits. Each respective shifter circuit receives the first product value of a corresponding multiplier circuit and left shifts the corresponding product value by the first predetermined number of bits to form a respective second product value. The adder circuit adds each respective second product value to form a partial-sum value represented by a fourth predetermined number of bits.
