17554483. STACKED TRANSISTORS HAVING AN ISOLATION REGION THEREBETWEEN AND A COMMON GATE ELECTRODE, AND RELATED FABRICATION METHODS simplified abstract (Samsung Electronics Co., Ltd.)

STACKED TRANSISTORS HAVING AN ISOLATION REGION THEREBETWEEN AND A COMMON GATE ELECTRODE, AND RELATED FABRICATION METHODS

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Seungchan Yun of Waterford NY (US)

Inchan Hwang of Schenectady NY (US)

Gunho Jo of Albany NY (US)

Jeonghyuk Yim of Halfmoon NY (US)

Byounghak Hong of Latham NY (US)

Kang-ill Seo of Latham NY (US)

Ming He of San Jose CA (US)

JaeHyun Park of Hwaseong-si (KR)

Mehdi Saremi of Danville CA (US)

Rebecca Park of Mountain View CA (US)

Harsono Simka of Saratoga CA (US)

Daewon Ha of Hwaseong-si (KR)

STACKED TRANSISTORS HAVING AN ISOLATION REGION THEREBETWEEN AND A COMMON GATE ELECTRODE, AND RELATED FABRICATION METHODS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17554483 titled 'STACKED TRANSISTORS HAVING AN ISOLATION REGION THEREBETWEEN AND A COMMON GATE ELECTRODE, AND RELATED FABRICATION METHODS

Simplified Explanation

The patent application describes a transistor device that includes a substrate, a lower transistor, an upper transistor, and an isolation region. The lower transistor has a lower gate and a lower channel region on the substrate, while the upper transistor has an upper gate and an upper channel region. The lower transistor is positioned between the upper transistor and the substrate, and an isolation region separates the lower and upper channel regions. The lower gate of the lower transistor contacts the upper gate of the upper transistor.

• The patent application describes a transistor device with a unique structure and configuration.
• The device includes a lower transistor and an upper transistor, both with their respective gates and channel regions.
• An isolation region is present to separate the channel regions of the lower and upper transistors.
• The lower gate of the lower transistor is in contact with the upper gate of the upper transistor.

Potential Applications

• This transistor device can be used in various electronic devices and circuits.
• It can be utilized in integrated circuits, microprocessors, and other semiconductor devices.

Problems Solved

• The device addresses the need for improved transistor structures and configurations.
• It solves the problem of isolating the channel regions of different transistors on a substrate.

Benefits

• The unique structure of the device allows for improved performance and functionality.
• The contact between the lower and upper gates enables efficient control of the transistors.
• The isolation region ensures proper separation and functioning of the channel regions.

Original Abstract Submitted

Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.