17551998. VIA ALIGNMENT IN SINGLE DAMASCENE STRUCTURE simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

From WikiPatents
Jump to navigation Jump to search

VIA ALIGNMENT IN SINGLE DAMASCENE STRUCTURE

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

CHANRO Park of CLIFTON PARK NY (US)

Koichi Motoyama of Clifton Park NY (US)

Hsueh-Chung Chen of Cohoes NY (US)

VIA ALIGNMENT IN SINGLE DAMASCENE STRUCTURE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17551998 titled 'VIA ALIGNMENT IN SINGLE DAMASCENE STRUCTURE

Simplified Explanation

The abstract describes an interconnect structure for electronic devices, specifically focusing on the design of metal lines and vias. The structure includes multiple metal line levels and a via line level in between. The via line level consists of a via interlevel dielectric surrounding a via stack. The via stack comprises an interface metal portion, a via intralevel dielectric, and a cap metal portion. The interface metal portion connects the first metal line, while the cap metal portion connects the second metal line.

  • The interconnect structure includes metal lines and vias for electronic devices.
  • It consists of multiple metal line levels and a via line level in between.
  • The via line level comprises a via interlevel dielectric and a via stack.
  • The via stack includes an interface metal portion, a via intralevel dielectric, and a cap metal portion.
  • The interface metal portion connects the first metal line, while the cap metal portion connects the second metal line.
  • The length of the interface metal portion of the via is greater than its width.

Potential applications of this technology:

  • Integrated circuits and semiconductor devices
  • Microprocessors and computer chips
  • Electronic devices such as smartphones, tablets, and laptops

Problems solved by this technology:

  • Efficient and reliable interconnection between metal lines in electronic devices
  • Minimizing signal loss and interference
  • Improving overall performance and functionality of electronic devices

Benefits of this technology:

  • Enhanced electrical conductivity and signal transmission
  • Reduced resistance and capacitance in interconnects
  • Improved reliability and longevity of electronic devices
  • Higher performance and faster data transfer speeds


Original Abstract Submitted

An interconnect structure that in one embodiment can include a first metal line level having a first metal line, a second metal line level having a second metal line, and a via line level present between the first and second metal line levels. The via line level includes a via interlevel dielectric surrounding a via stack. The via stack may include an interface metal portion that is in contact with the first metal line, a via intralevel dielectric on the interface metal portion, and a cap metal portion in contact with the second metal line and extending through the via intralevel dielectric into contact with the interface metal portion. In some embodiments, the length of the interface metal portion of the via is greater than a width of the interface metal portion of the via stack.