17551541. DIELECTRIC PLANARIZATION USING A METAL OVERBURDEN WITH ETCH-STOP LAYERS simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

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DIELECTRIC PLANARIZATION USING A METAL OVERBURDEN WITH ETCH-STOP LAYERS

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Raghuveer Reddy Patlolla of Guilderland NY (US)

Donald Francis Canaperi of Bridgewater CT (US)

Cornelius Brown Peethala of Slingerlands NY (US)

Chih-Chao Yang of Glenmont NY (US)

DIELECTRIC PLANARIZATION USING A METAL OVERBURDEN WITH ETCH-STOP LAYERS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17551541 titled 'DIELECTRIC PLANARIZATION USING A METAL OVERBURDEN WITH ETCH-STOP LAYERS

Simplified Explanation

The patent application describes a method for forming portions of a multi-layer integrated circuit (IC) structure. The method involves several steps, including the formation of a back-end-of-line (BEOL) layer with a specific topography, the creation of an etch-stop layer over the BEOL layer, and the deposition of a metal layer on top of the etch-stop layer. Two planarization operations are then performed to remove portions of the metal and the etch-stop layer.

  • The method involves forming a back-end-of-line (BEOL) layer with a specific topography.
  • An etch-stop layer is created over the BEOL layer to control the planarization process.
  • A metal layer is deposited on top of the etch-stop layer.
  • The first planarization operation is applied to remove a portion of the metal, with the etch-stop layer acting as a stopping point.
  • The second planarization operation is then performed to remove the etch-stop layer and another portion of the metal.

Potential applications of this technology:

  • Integrated circuit manufacturing: The method described in the patent application can be used in the fabrication of multi-layer integrated circuits, which are widely used in various electronic devices.
  • Semiconductor industry: The method can be applied in the production of advanced semiconductor devices, enabling the creation of complex circuit structures.

Problems solved by this technology:

  • Control of planarization: The etch-stop layer helps to control the planarization process, ensuring precise removal of specific portions of the metal layer.
  • Topography management: The method allows for the formation of a BEOL layer with a desired topography, which is crucial for the proper functioning of the integrated circuit.

Benefits of this technology:

  • Improved circuit performance: The precise removal of metal and the management of topography contribute to the overall performance and reliability of the integrated circuit.
  • Enhanced manufacturing efficiency: The method provides a systematic approach to forming portions of a multi-layer IC structure, streamlining the manufacturing process and reducing potential errors.


Original Abstract Submitted

Embodiments of the invention include a method of forming portions of a multi-layer integrated circuit (IC) structure. The method includes forming a back-end-of-line (BEOL) layer having a BEOL layer topography. An etch-stop layer is formed over the BEOL layer topography. A metal is formed over the etch-stop layer. A first planarization operation is applied to remove a first portion of the metal. The etch-stop layer is used to stop the first planarization operation. A second planarization operation is applied to remove the etch-stop layer and a second portion of the metal.

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