17550436. ENABLEMENT OF SAMPLING-OPTIMIZATION FOR GATE-LEVEL SIMULATION simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

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ENABLEMENT OF SAMPLING-OPTIMIZATION FOR GATE-LEVEL SIMULATION

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Hiroshi Horii of Tokyo (JP)

Ikko Hamamura of Tokyo (JP)

ENABLEMENT OF SAMPLING-OPTIMIZATION FOR GATE-LEVEL SIMULATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17550436 titled 'ENABLEMENT OF SAMPLING-OPTIMIZATION FOR GATE-LEVEL SIMULATION

Simplified Explanation

The patent application describes systems and methods for optimizing gate-level simulations in quantum computing. Here are the key points:

  • The system includes a processor that executes computer executable components stored in memory.
  • A cache component is used to store the state of a set of qubits within a quantum gate-level simulation after they are reset.
  • An avoidance component is implemented to prevent duplicate simulation of quantum gates by utilizing the cached state of the qubits.
  • The cached state represents a quantum state produced by a previously simulated quantum gate.

Potential applications of this technology:

  • Quantum computing simulations: The innovation can be applied to optimize gate-level simulations in quantum computing, allowing for more efficient and accurate simulations of quantum systems.
  • Quantum algorithm development: Researchers and developers can use this technology to improve the development and testing of quantum algorithms by reducing the computational resources required for simulations.

Problems solved by this technology:

  • Reducing computational resources: By avoiding duplicate simulations, the technology helps to minimize the computational resources needed for gate-level simulations, making them more efficient.
  • Improving simulation accuracy: The use of cached states allows for a more accurate representation of quantum states, leading to more reliable simulations.

Benefits of this technology:

  • Increased efficiency: The avoidance of duplicate simulations saves computational time and resources, enabling faster and more efficient gate-level simulations.
  • Enhanced accuracy: By utilizing cached states, the technology improves the accuracy of simulations, providing more reliable results for quantum computing research and development.


Original Abstract Submitted

Systems, computer-implemented methods, and computer program products to facilitate sampling-optimization for gate-level simulations are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise a cache component that caches a state of a set of qubits within a quantum gate-level simulation after the set of qubits are reset. According to another embodiment the computer executable components further comprise an avoidance component that prevents duplicated simulation of quantum gates in the quantum gate-level simulation by using the cached state of the set of qubits to represent a quantum state produced by a previously simulated quantum gate.