17548751. CO-INTEGRATING GATE-ALL-AROUND NANOSHEET TRANSISTORS AND COMB NANOSHEET TRANSISTORS simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)
CO-INTEGRATING GATE-ALL-AROUND NANOSHEET TRANSISTORS AND COMB NANOSHEET TRANSISTORS
Organization Name
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor(s)
Julien Frougier of Albany NY (US)
Nicolas Loubet of Guilderland NY (US)
Ruilong Xie of Niskayuna NY (US)
Miaomiao Wang of Albany NY (US)
Veeraraghavan S. Basker of Schenectady NY (US)
CO-INTEGRATING GATE-ALL-AROUND NANOSHEET TRANSISTORS AND COMB NANOSHEET TRANSISTORS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17548751 titled 'CO-INTEGRATING GATE-ALL-AROUND NANOSHEET TRANSISTORS AND COMB NANOSHEET TRANSISTORS
Simplified Explanation
The patent application describes a method for integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip or substrate. This involves forming a GAA nanosheet device in one region and a comb-nanosheet device in another region of the substrate.
- GAA nanosheet device is formed in one region of the substrate
- GAA nanosheet device includes a first and second nanosheet stack with a specific spacing distance between them
- Comb-nanosheet device is formed in another region of the substrate
- Comb-nanosheet device includes a third and fourth nanosheet stack with a smaller spacing distance between them compared to the GAA nanosheet device
Potential applications of this technology:
- Semiconductor manufacturing
- Integrated circuits
- Nanoelectronics
Problems solved by this technology:
- Co-integrating GAA nanosheets and comb-nanosheets on the same chip or substrate
- Achieving different fin spacing distances for different nanosheet devices
Benefits of this technology:
- Enables the integration of different nanosheet devices on a single chip or substrate
- Provides flexibility in designing and optimizing nanosheet structures
- Enhances the performance and efficiency of semiconductor devices
Original Abstract Submitted
Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment of the invention, a GAA nanosheet device is formed in a first region of a substrate. The GAA nanosheet device includes a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack. A comb-nanosheet device is formed in a second region of a substrate. The comb-nanosheet device includes a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack that is less than the first fin spacing distance.
