17545074. Contact and Isolation in Monolithically Stacked VTFET simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

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Contact and Isolation in Monolithically Stacked VTFET

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Chen Zhang of Guilderland NY (US)

Ruilong Xie of Niskayuna NY (US)

Lan Yu of Voorheesville NY (US)

Kangguo Cheng of Schenectady NY (US)

Contact and Isolation in Monolithically Stacked VTFET - A simplified explanation of the abstract

This abstract first appeared for US patent application 17545074 titled 'Contact and Isolation in Monolithically Stacked VTFET

Simplified Explanation

The abstract describes a patent application for monolithically stacked VTFET (Vertical Tunneling Field Effect Transistor) devices with increased contact area and dielectric isolation. The stacked VTFET device includes a bottom VTFET and a top VTFET, each having source/drain regions interconnected by a vertical fin channel and a gate stack alongside the fin channel. The source/drain contacts are in direct contact with more than one surface of the source/drain regions.

  • Monolithically stacked VTFET devices with increased contact area and dielectric isolation are provided.
  • The stacked VTFET device includes a bottom VTFET and a top VTFET, each having source/drain regions interconnected by a vertical fin channel and a gate stack.
  • The source/drain contacts are in direct contact with more than one surface of the source/drain regions.
  • A method of forming a stacked VTFET device is also provided.

Potential Applications

  • This technology can be used in the field of semiconductor devices and integrated circuits.
  • It can be applied in various electronic devices such as smartphones, tablets, and computers.
  • The increased contact area and dielectric isolation can improve the performance and efficiency of these devices.

Problems Solved

  • The technology solves the problem of limited contact area between the source/drain contacts and the source/drain regions in stacked VTFET devices.
  • It also addresses the issue of inadequate dielectric isolation between the source/drain contacts and the surrounding structures.
  • By providing increased contact area and improved dielectric isolation, the technology enhances the overall performance and reliability of the devices.

Benefits

  • The increased contact area between the source/drain contacts and the source/drain regions improves the electrical connection and conductivity.
  • The improved dielectric isolation prevents leakage and interference between the source/drain contacts and the surrounding structures.
  • The technology enhances the performance, efficiency, and reliability of stacked VTFET devices, leading to better overall device performance.


Original Abstract Submitted

Monolithically stacked VTFET devices having source/drain contacts with increased contact area and dielectric isolation are provided. In one aspect, a stacked VTFET device includes: at least a bottom VTFET below a top VTFET, wherein the bottom VTFET and the top VTFET each includes source/drain regions interconnected by a vertical fin channel, and a gate stack alongside the vertical fin channel; and source/drain contacts to the source/drain regions, wherein at least one of the source/drain contacts is in direct contact with more than one surface of a given one of the source/drain regions. A stacked VTFET device having at least a bottom VTFET below a top VTFET, and a bottom VTFET below a top VTFET, and a method of forming a stacked VTFET device are also provided.

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