17545073. BURIED POWER RAIL AT TIGHT CELL-TO-CELL SPACE simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)
Contents
BURIED POWER RAIL AT TIGHT CELL-TO-CELL SPACE
Organization Name
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor(s)
Ruilong Xie of Niskayuna NY (US)
SOMNATH Ghosh of CLIFTON PARK NY (US)
Kisik Choi of Watervliet NY (US)
Kevin Shawn Petrarca of Newburgh NY (US)
BURIED POWER RAIL AT TIGHT CELL-TO-CELL SPACE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17545073 titled 'BURIED POWER RAIL AT TIGHT CELL-TO-CELL SPACE
Simplified Explanation
The patent application describes a semiconductor device that includes two buried power rails (BPRs) with different sizes. The first BPR is larger and is placed through etch stop layers, while the second BPR is in direct contact with the first BPR. The first BPR connects to a via-to buried power rail (VBPR) contact, and source/drain contacts (CA) are placed adjacent to the VBPR contact. These components collectively define middle-of-line (MOL) components. Back-end-of-line (BEOL) components are then constructed next to the MOL components, and both MOL and BEOL components are bonded to a carrier wafer. The second BPR is constructed on the carrier wafer.
- A semiconductor device with two buried power rails (BPRs) of different sizes is described.
- The first BPR is larger and goes through etch stop layers, while the second BPR is in direct contact with the first BPR.
- The first BPR connects to a via-to buried power rail (VBPR) contact, and source/drain contacts (CA) are placed nearby.
- These components collectively define middle-of-line (MOL) components.
- Back-end-of-line (BEOL) components are constructed adjacent to the MOL components.
- Both MOL and BEOL components are bonded to a carrier wafer.
- The second BPR is constructed on the carrier wafer.
Potential Applications
- Semiconductor manufacturing
- Integrated circuit design
- Power management systems
Problems Solved
- Efficient power distribution in semiconductor devices
- Improved integration of MOL and BEOL components
- Enhanced performance and reliability of power management systems
Benefits
- More efficient power distribution
- Higher integration of components
- Improved performance and reliability of power management systems
Original Abstract Submitted
A semiconductor device includes a first buried power rail (BPR) disposed through etch stop layers and a second BPR disposed in direct contact with the first BPR, where the first BPR has a larger critical dimension (CD) than the second BPR. A bottom surface of the first BPR directly contacts a via-to buried power rail (VBPR) contact. Source/drain contacts (CA) are disposed adjacent the VBPR contact and source/drain regions collectively defining middle-of-line (MOL) components. Back-end-of-line (BEOL) components are then constructed adjacent to the MOL components, and the MOL and BEOL components bond to a carrier wafer. The second BPR is then constructed on the carrier wafer.
