17544136. SUBTRACTIVE LINE WITH DAMASCENE TOP VIA simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

SUBTRACTIVE LINE WITH DAMASCENE TOP VIA

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Chanro Park of Clifton Park NY (US)

Koichi Motoyama of Clifton Park NY (US)

Hsueh-Chung Chen of Cohoes NY (US)

Chih-Chao Yang of Glenmont NY (US)

SUBTRACTIVE LINE WITH DAMASCENE TOP VIA - A simplified explanation of the abstract

This abstract first appeared for US patent application 17544136 titled 'SUBTRACTIVE LINE WITH DAMASCENE TOP VIA

Simplified Explanation

The patent application describes semiconductor devices and methods for forming semiconductor structures. Here are the key points:

• The method involves forming a subtractive line using a bottom metal layer and a sacrificial hard mask.
• A scaffolding material is deposited around the subtractive line.
• A via mask is formed over a via portion of the sacrificial hard mask and the scaffolding material.
• The sacrificial hard mask not covered by the via mask is etched to create a sacrificial via.
• The via mask and scaffolding material are removed.
• A low-κ layer is deposited around the subtractive line and sacrificial via.
• The sacrificial via is removed to create a via hole within the low-κ layer.
• A top via is formed by metallizing the via hole.

Potential applications of this technology:

• Semiconductor devices manufacturing
• Integrated circuits production
• Electronics industry

Problems solved by this technology:

• Provides a method for forming via holes in low-κ layers
• Enables the creation of complex semiconductor structures
• Improves the efficiency and reliability of semiconductor devices

Benefits of this technology:

• Allows for precise formation of via holes
• Enhances the performance of semiconductor devices
• Reduces the risk of defects and failures in the manufacturing process

Original Abstract Submitted

Embodiments disclosed herein describe semiconductor devices that include semiconductor structures and methods of forming the semiconductor structures. The methods may include forming a subtractive line from a bottom metal layer and a sacrificial hard mask above the bottom metal layer, depositing a scaffolding material around the subtractive line, forming a via mask over a via portion of the sacrificial hard mask and the scaffolding material, etching the sacrificial hard mask that is not covered by the via mask, to form a sacrificial via, removing the via mask and the scaffolding material, depositing a low-κ layer around the subtractive line and the sacrificial via, removing the sacrificial via to form a via hole within the low-κ layer, and forming a top via by metallizing the via hole.