SELECTIVE DIPOLE LAYER MODULATION USING TWO-STEP INNER SPACER

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

SELECTIVE DIPOLE LAYER MODULATION USING TWO-STEP INNER SPACER - A simplified explanation of the abstract

This abstract first appeared for US patent application 17542662 titled 'SELECTIVE DIPOLE LAYER MODULATION USING TWO-STEP INNER SPACER

Simplified Explanation

The patent application describes a method for selectively modulating a dipole layer in a nanosheet stack. This method allows for the creation of multiple work function gate stacks with multiple threshold voltages without the need for metal gate patterning.

The method involves forming a nanosheet stack over a substrate, consisting of alternating layers of different semiconductor materials.
The first and second semiconductor materials are etched to create indentations, and first inner spacers are formed within these indentations.
The residual of the first semiconductor material is removed, and second inner spacers are formed adjacent to the first inner spacers.
The remaining first and second semiconductor materials are removed, creating openings adjacent to the first inner spacers.
These openings are then filled with a dipole layer stack, creating multiple work function gate stacks with multiple threshold voltages.

Potential applications of this technology:

Semiconductor manufacturing: This method can be used in the production of semiconductor devices, allowing for the creation of multiple gate stacks with different threshold voltages.
Integrated circuits: The ability to modulate the dipole layer in a nanosheet stack can improve the performance and functionality of integrated circuits.

Problems solved by this technology:

Simplified manufacturing process: The method eliminates the need for metal gate patterning, reducing complexity and cost in semiconductor manufacturing.
Enhanced device performance: The ability to create multiple gate stacks with different threshold voltages allows for improved control and optimization of semiconductor devices.

Benefits of this technology:

Increased flexibility: The method enables the creation of multiple gate stacks with different threshold voltages, providing greater flexibility in device design and optimization.
Cost and time savings: By eliminating the need for metal gate patterning, the manufacturing process becomes simpler and more efficient, leading to cost and time savings.

Original Abstract Submitted

A method is presented for selective dipole layer modulation. The method includes forming a nanosheet stack over a substrate, the nanosheet stack including alternating layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material, etching the first and second semiconductor materials to define indentations, forming first inner spacers within the indentations, removing residual of the first semiconductor material, forming second inner spacers adjacent the first inner spacers, removing the remaining first and second semiconductor materials to define openings adjacent the first inner spacers, and filling the openings with a dipole layer stack to create multiple work function gate stacks with multiple threshold voltages (Vt) without metal gate patterning due to pinch-off exhibited between the first inner spacers and a nanosheet channel.

17542662. SELECTIVE DIPOLE LAYER MODULATION USING TWO-STEP INNER SPACER simplified abstract (INTERNATIONAL BUSINESS MACHINES CORPORATION)

Contents

SELECTIVE DIPOLE LAYER MODULATION USING TWO-STEP INNER SPACER

Organization Name

Inventor(s)