17534485. MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) WITH PRESERVED UNDERLYING DIELECTRIC LAYER simplified abstract (International Business Machines Corporation)

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MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) WITH PRESERVED UNDERLYING DIELECTRIC LAYER

Organization Name

International Business Machines Corporation

Inventor(s)

Ashim Dutta of Clifton Park NY (US)

Shyng-Tsong Chen of Rensselaer NY (US)

Terry A. Spooner of Mechanicville NY (US)

Chih-Chao Yang of Glenmont NY (US)

MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) WITH PRESERVED UNDERLYING DIELECTRIC LAYER - A simplified explanation of the abstract

This abstract first appeared for US patent application 17534485 titled 'MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) WITH PRESERVED UNDERLYING DIELECTRIC LAYER

Simplified Explanation

The patent application describes a method for fabricating a semiconductor device with embedded memory and non-memory interconnect structures. Here are the key points:

  • The method starts with a substrate that has both memory and non-memory interconnect structures.
  • The memory interconnect structure consists of metal interconnects formed in a dielectric material.
  • A dielectric cap layer is then formed on the exposed surfaces of both the memory and non-memory areas.
  • A bottom metal contact is created in a trench in the dielectric cap layer, specifically on a first metal interconnect of the memory interconnect structure.
  • A memory element stack pillar is formed on top of the bottom metal contact.
  • A non-conformal deposition process is used to form a dielectric layer on the exposed surfaces of both the memory and non-memory areas.
  • The dielectric layer is then removed from the sidewalls of the memory element stack pillar.

Potential applications of this technology:

  • Semiconductor manufacturing industry
  • Memory chip fabrication
  • Integrated circuit production

Problems solved by this technology:

  • Efficient fabrication of semiconductor devices with embedded memory and non-memory interconnect structures
  • Improved performance and reliability of memory elements

Benefits of this technology:

  • Simplified fabrication process
  • Enhanced integration of memory and non-memory interconnect structures
  • Improved performance and reliability of semiconductor devices


Original Abstract Submitted

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in dielectric material. A dielectric cap layer is formed on exposed surfaces of the memory area and the non-memory area. A bottom metal contact is formed on a first metal interconnect of the memory area interconnect structure, the bottom metal contact in a trench in the dielectric cap layer. A memory element stack pillar is formed on the bottom metal contact. A dielectric layer is formed on exposed surfaces of the memory area and the non-memory area utilizing a non-conformal deposition process. The dielectric layer is removed from sidewalls of the memory element stack pillar.

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