17533970. SYSTEMS AND METHODS FOR ACCELERATING THE COMPUTATION OF THE RECIPROCAL FUNCTION AND THE RECIPROCAL-SQUARE-ROOT FUNCTION simplified abstract (Microsoft Technology Licensing, LLC)

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SYSTEMS AND METHODS FOR ACCELERATING THE COMPUTATION OF THE RECIPROCAL FUNCTION AND THE RECIPROCAL-SQUARE-ROOT FUNCTION

Organization Name

Microsoft Technology Licensing, LLC

Inventor(s)

Jinwen Xi of Sunnyvale CA (US)

Ming Liu of Kirkland WA (US)

Eric Chung of Woodinville WA (US)

SYSTEMS AND METHODS FOR ACCELERATING THE COMPUTATION OF THE RECIPROCAL FUNCTION AND THE RECIPROCAL-SQUARE-ROOT FUNCTION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17533970 titled 'SYSTEMS AND METHODS FOR ACCELERATING THE COMPUTATION OF THE RECIPROCAL FUNCTION AND THE RECIPROCAL-SQUARE-ROOT FUNCTION

Simplified Explanation

The abstract describes a field programmable gate array (FPGA) that includes a configurable interconnect fabric connecting multiple logic blocks. The FPGA is designed to implement a reciprocal function data path.

  • The FPGA includes a mantissa computation stage that handles the mantissa component of the reciprocal function data path.
  • The mantissa computation stage partitions the M-bit mantissa component of an input floating-point value into L most-significant bits and M-L least significant bits.
  • It looks up a slope value and an offset value from a reciprocal lookup table based on the L most significant bits.
  • The mantissa computation stage computes the output mantissa component of the output floating-point value by multiplying the slope value by the M-L least significant bits and adding the offset value to the product.
  • The FPGA also includes an exponent computation stage that computes the output exponent component of the output floating-point value.
  • The computation of the output exponent component involves negating the exponent component of the input floating-point value.

Potential applications of this technology:

  • High-performance computing: The FPGA can be used in applications that require fast and efficient computation of reciprocal functions, such as scientific simulations, data analysis, and machine learning.
  • Signal processing: The FPGA can be utilized in signal processing applications that involve complex mathematical operations, such as audio and video processing, image recognition, and communication systems.
  • Cryptography: The FPGA can be employed in cryptographic algorithms that require efficient computation of reciprocal functions, such as encryption and decryption processes.

Problems solved by this technology:

  • Efficient computation: The FPGA provides a configurable and optimized solution for implementing reciprocal functions, allowing for faster and more efficient computation compared to traditional software-based approaches.
  • Resource utilization: The configurable interconnect fabric and logic blocks of the FPGA enable efficient utilization of hardware resources, reducing the overall cost and complexity of implementing reciprocal functions.

Benefits of this technology:

  • High performance: The FPGA's ability to implement the reciprocal function data path efficiently results in faster computation and improved overall system performance.
  • Flexibility: The configurable interconnect fabric and logic blocks allow for customization and adaptation to different reciprocal function requirements, making the FPGA suitable for a wide range of applications.
  • Cost-effective: By utilizing hardware acceleration, the FPGA offers a cost-effective solution for implementing reciprocal functions, reducing the need for expensive dedicated hardware or extensive software optimization.


Original Abstract Submitted

A field programmable gate array (FPGA) including a configurable interconnect fabric connecting a plurality of logic blocks configured to implement a reciprocal function data path including: a mantissa computation stage including a mantissa portion of the reciprocal function data path configured to: partition an M-bit mantissa component of an input floating-point value into L most-significant bits and M-L least significant bits; lookup a slope value and an offset value, based on the L most significant bits, from a reciprocal lookup table; and compute an output mantissa component of an output floating-point value by multiplying the slope value by the M-L least significant bits to compute a product and adding the offset value to the product; and an exponent computation stage configured to compute an output exponent component of the output floating-point value, the computing the output exponent component including negating an exponent component of the input floating-point value.