17532754. PACKAGE COMPRISING CHANNEL INTERCONNECTS LOCATED BETWEEN SOLDER INTERCONNECTS simplified abstract (QUALCOMM Incorporated)
PACKAGE COMPRISING CHANNEL INTERCONNECTS LOCATED BETWEEN SOLDER INTERCONNECTS
Organization Name
Inventor(s)
Aniket Patil of San Diego CA (US)
Durodami Lisk of San Diego CA (US)
Hong Bok We of San Diego CA (US)
Charles David Paynter of Encinitas CA (US)
PACKAGE COMPRISING CHANNEL INTERCONNECTS LOCATED BETWEEN SOLDER INTERCONNECTS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17532754 titled 'PACKAGE COMPRISING CHANNEL INTERCONNECTS LOCATED BETWEEN SOLDER INTERCONNECTS
Simplified Explanation
The abstract describes a device that consists of two packages connected by solder interconnects. The first package includes a substrate with interconnects and an integrated device. The second package includes a substrate with interconnects, two integrated devices, and channel interconnects.
- The device has two packages connected by solder interconnects.
- The first package has a substrate with interconnects and an integrated device.
- The second package has a substrate with interconnects, two integrated devices, and channel interconnects.
- The channel interconnects are located between the solder interconnects.
Potential Applications
- This device could be used in electronic systems that require multiple integrated devices to be connected.
- It could be used in high-performance computing systems or data centers.
Problems Solved
- This device solves the problem of connecting multiple integrated devices in a compact and efficient manner.
- It provides a solution for interconnecting different packages and substrates.
Benefits
- The device allows for efficient communication between integrated devices.
- It enables compact and space-saving designs.
- It provides a reliable and robust connection between packages and substrates.
Original Abstract Submitted
A device comprising a first package and a second package coupled to the first package through a first plurality of solder interconnects. The first package includes a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located between solder interconnects from the second plurality of solder interconnects.
