17532310. PARTIAL SUBTRACTIVE SUPERVIA ENABLING HYPER-SCALING simplified abstract (International Business Machines Corporation)

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PARTIAL SUBTRACTIVE SUPERVIA ENABLING HYPER-SCALING

Organization Name

International Business Machines Corporation

Inventor(s)

Sagarika Mukesh of ALBANY NY (US)

Nicholas Anthony Lanzillo of Wynantskill NY (US)

PARTIAL SUBTRACTIVE SUPERVIA ENABLING HYPER-SCALING - A simplified explanation of the abstract

This abstract first appeared for US patent application 17532310 titled 'PARTIAL SUBTRACTIVE SUPERVIA ENABLING HYPER-SCALING

Simplified Explanation

The abstract describes a semiconductor device that includes a supervia connecting non-adjacent interconnect wiring. The supervia is formed using both subtractive etching and damascene processing techniques. The lower section and upper section of the supervia have a cone-shaped configuration, with the distal end of the lower section being non-obtuse. The lower section is formed in a V0 level and the upper section is formed in a M1/V1 metallization level.

  • The semiconductor device includes a supervia connecting non-adjacent interconnect wiring.
  • The supervia is formed using subtractive etching and damascene processing techniques.
  • The lower section and upper section of the supervia have a cone-shaped configuration.
  • The distal end of the lower section is non-obtuse.
  • The lower section is formed in a V0 level and the upper section is formed in a M1/V1 metallization level.

Potential Applications

  • Semiconductor manufacturing
  • Integrated circuits
  • Electronics industry

Problems Solved

  • Efficiently connecting non-adjacent interconnect wiring
  • Improving the reliability and performance of semiconductor devices

Benefits

  • Enhanced connectivity between non-adjacent interconnect wiring
  • Improved reliability and performance of semiconductor devices
  • More efficient manufacturing process


Original Abstract Submitted

A semiconductor device includes an upper section of a supervia formed via subtractive etching and a lower section of the supervia formed via damascene processing. The supervia connects non-adjacent interconnect wiring. The lower section and the upper section of the supervia each define a generally cone-shaped configuration. A distal end of the lower section of the supervia is non-obtuse. Moreover, the lower section of the supervia is formed in a V0 level and the upper section of the supervia is formed in a M1/V1 metallization level.