17531837. BURIED POWER RAIL AFTER REPLACEMENT METAL GATE simplified abstract (International Business Machines Corporation)

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BURIED POWER RAIL AFTER REPLACEMENT METAL GATE

Organization Name

International Business Machines Corporation

Inventor(s)

Devika Sarkar Grant of Rensselaer NY (US)

Sagarika Mukesh of Albany NY (US)

Kisik Choi of Watervliet NY (US)

SOMNATH Ghosh of Clifton Park NY (US)

Ruilong Xie of Niskayuna NY (US)

BURIED POWER RAIL AFTER REPLACEMENT METAL GATE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17531837 titled 'BURIED POWER RAIL AFTER REPLACEMENT METAL GATE

Simplified Explanation

The patent application describes semiconductor structures that include a buried power rail (BPR) region, which is isolated from the first and second field-effect transistor (FET) regions and their respective source/drain (S/D) connections by dielectric liners. The BPR region is connected to the second S/D through a contact on its lateral side. This arrangement allows for the formation of the BPR after the gates and S/Ds, avoiding any issues during annealing processes.

  • Semiconductor structures with a buried power rail (BPR) region
  • BPR region is isolated from FET regions and S/D connections by dielectric liners
  • BPR region is connected to the second S/D through a contact on its lateral side
  • Formation of BPR after gates and S/Ds to avoid problems during annealing processes

Potential Applications

  • Semiconductor manufacturing
  • Integrated circuits
  • Power management systems

Problems Solved

  • Avoiding issues during annealing processes caused by the buried power rail (BPR)
  • Isolating the BPR region from FET regions and S/D connections

Benefits

  • Simplified manufacturing process
  • Improved reliability of semiconductor structures
  • Enhanced power management capabilities


Original Abstract Submitted

Embodiments herein include semiconductor structures with a first source/drain (S/D) connected to a first field-effect transistor (FET) region, a second S/D connected to a second FET region, and a buried power rail (BPR) region. The BPR region may include a BPR, a first dielectric liner lining a first lateral side of the BPR region, and a second dielectric liner lining a second lateral side. The first dielectric liner isolates the BPR from the first FET region and the first S/D, and the second dielectric liner isolates the BPR from the second FET region. Embodiments may also include a contact electrically connecting the second S/D and the BPR through a second lateral side of the BPR region. The liners enable the BPR to be formed after the formation of gates and the S/Ds, so that the BPR does not cause problems during annealing processes of the gates and the S/Ds.

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