17529215. TUNABLE TRUE RANDOM NUMBER GENERATOR simplified abstract (International Business Machines Corporation)

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TUNABLE TRUE RANDOM NUMBER GENERATOR

Organization Name

International Business Machines Corporation

Inventor(s)

Kangguo Cheng of Schenectady NY (US)

TUNABLE TRUE RANDOM NUMBER GENERATOR - A simplified explanation of the abstract

This abstract first appeared for US patent application 17529215 titled 'TUNABLE TRUE RANDOM NUMBER GENERATOR

Simplified Explanation

The abstract describes a tunable true random number generator (TTRNG) apparatus that uses transistors and resistive memory cells to generate random numbers.

  • The TTRNG apparatus includes a clock pulse source, a logic voltage source, an output terminal, and a ground terminal.
  • The transistors are connected between the clock pulse source, logic voltage source, output terminal, and ground terminal.
  • At each clock pulse, the transistors deliver either logic voltage "1" or ground voltage "0" to the output terminal.
  • The resistive memory cells are connected with the transistors and the logic voltage source or ground terminal.
  • The resistances of the resistive memory cells can be adjusted to change the probability of the transistors delivering "1" to the output terminal.

Potential applications of this technology:

  • Random number generation for cryptographic systems
  • Simulation and modeling in scientific research
  • Gaming and gambling applications
  • Statistical analysis and sampling

Problems solved by this technology:

  • Generating true random numbers that are not predictable or biased
  • Providing a tunable solution to adjust the probability of generating "1" or "0" in the random number sequence

Benefits of this technology:

  • High-quality random number generation
  • Adjustable probability for specific applications
  • Reliable and secure random number generation for cryptographic systems


Original Abstract Submitted

A tunable true random number generator (TTRNG) apparatus includes a clock pulse source; a logic voltage source; an output terminal; a ground terminal; and a plurality of transistors that are connected between the clock pulse source, the logic voltage source, the output terminal, and the ground terminal. Also included are resistive memory cells that are connected with the plurality of transistors and at least one of the logic voltage source and the ground terminal. The plurality of transistors are connected such that, at each clock pulse, the plurality of transistors deliver either logic voltage “1” or ground voltage “0” to the output terminal. The resistive memory cells are connected such that a ones probability of the plurality of transistors delivering “1” to the output terminal can be adjusted by changing the resistances of the resistive memory cells.

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