17528858. BOTTOM DIELECTRIC ISOLATION INTEGRATION WITH BURIED POWER RAIL simplified abstract (International Business Machines Corporation)

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BOTTOM DIELECTRIC ISOLATION INTEGRATION WITH BURIED POWER RAIL

Organization Name

International Business Machines Corporation

Inventor(s)

Ruilong Xie of Niskayuna NY (US)

Julien Frougier of Albany NY (US)

Takeshi Nogami of Schenectady NY (US)

Roy R. Yu of Poughkeepsie NY (US)

Balasubramanian S. Pranatharthi Haran of Santa Clara CA (US)

BOTTOM DIELECTRIC ISOLATION INTEGRATION WITH BURIED POWER RAIL - A simplified explanation of the abstract

This abstract first appeared for US patent application 17528858 titled 'BOTTOM DIELECTRIC ISOLATION INTEGRATION WITH BURIED POWER RAIL

Simplified Explanation

The abstract describes a semiconductor device that includes a protective liner, a buried power rail, a source/drain, and a source/drain contact.

  • The protective liner is present on both sides of the buried power rail.
  • The buried power rail is located on a first portion of the protective liner.
  • The source/drain is positioned on a second portion of the protective liner, away from the buried power rail.
  • The source/drain contact is in electrical communication with the buried power rail.

Potential Applications

  • This semiconductor device can be used in various electronic devices such as smartphones, tablets, and computers.
  • It can be utilized in power management circuits, memory devices, and other integrated circuits.

Problems Solved

  • The protective liner provides insulation and protection to the buried power rail and source/drain.
  • The offset positioning of the source/drain from the buried power rail helps prevent interference or short circuits.
  • The source/drain contact ensures proper electrical connection between the source/drain and the buried power rail.

Benefits

  • The protective liner enhances the reliability and durability of the semiconductor device.
  • The buried power rail allows for efficient power distribution within the device.
  • The offset source/drain positioning and source/drain contact contribute to improved performance and reduced electrical issues.


Original Abstract Submitted

A semiconductor device is provided. The semiconductor device includes a protective liner, and a buried power rail on a first portion of the protective liner, wherein the protective liner is on opposite sides of the buried power rail. The semiconductor device further includes a source/drain on a second portion of the protective liner, wherein the source/drain is offset from the buried power rail, and a source/drain contact on the source/drain and in electrical communication with the buried power rail.

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