17527355. MULTI-VT NANOSHEET DEVICES simplified abstract (International Business Machines Corporation)

MULTI-VT NANOSHEET DEVICES

Organization Name

International Business Machines Corporation

Inventor(s)

Jingyun Zhang of Albany NY (US)

Takashi Ando of Eastchester NY (US)

ChoongHyun Lee of Chigasaki (JP)

Alexander Reznicek of Troy NY (US)

MULTI-VT NANOSHEET DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 17527355 titled 'MULTI-VT NANOSHEET DEVICES

Simplified Explanation

The abstract describes a method for achieving different gate threshold voltages in a group of field effect transistor (FET) devices without the need for patterning between nanosheet channels. Here are the key points:

• The method involves creating two sets of nanosheet stacks with different intersheet spacing.
• A high-k (HK) layer is deposited within both sets of nanosheet stacks.
• A material stack is then deposited, which, when annealed, forms a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second set.
• A dipole material is deposited and selectively diffused into the amorphous HK layer of the second set of nanosheet stacks.
• This selective diffusion of the dipole material provides different gate threshold voltages for the FET devices.

Potential applications of this technology:

• Integrated circuits: The ability to achieve different gate threshold voltages in FET devices can be useful for designing complex integrated circuits with varying performance requirements.
• Transistors: This method can be applied to improve the performance and efficiency of transistors used in various electronic devices.

Problems solved by this technology:

• Gate threshold voltage control: The method provides a way to achieve different gate threshold voltages without the need for complex patterning processes, simplifying the manufacturing process.
• Performance optimization: By controlling the gate threshold voltage, the performance and power consumption of FET devices can be optimized for specific applications.

Benefits of this technology:

• Simplified manufacturing process: The method eliminates the need for patterning between nanosheet channels, reducing complexity and cost in the manufacturing of FET devices.
• Performance customization: The ability to achieve different gate threshold voltages allows for customization of FET devices to meet specific performance requirements.
• Improved efficiency: By optimizing the gate threshold voltage, FET devices can operate more efficiently, leading to improved energy efficiency in electronic devices.

Original Abstract Submitted

A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates a crystallized HK layer in the first set of nanosheet stacks and an amorphous HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the second set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.