17523711. CLADDING AND CONDENSATION FOR STRAINED SEMICONDUCTOR NANORIBBONS simplified abstract (Intel Corporation)

From WikiPatents
Jump to navigation Jump to search

CLADDING AND CONDENSATION FOR STRAINED SEMICONDUCTOR NANORIBBONS

Organization Name

Intel Corporation

Inventor(s)

Ashish Agrawal of Hillsboro OR (US)

Anand Murthy of Portland OR (US)

Jack T. Kavalieros of Portland OR (US)

Rajat K. Paul of Portland OR (US)

Gilbert Dewey of Beaverton OR (US)

Susmita Ghose of Hillsboro OR (US)

Seung Hoon Sung of Portland OR (US)

CLADDING AND CONDENSATION FOR STRAINED SEMICONDUCTOR NANORIBBONS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17523711 titled 'CLADDING AND CONDENSATION FOR STRAINED SEMICONDUCTOR NANORIBBONS

Simplified Explanation

The patent application describes techniques for creating semiconductor devices with nanowires that have increased strain. This is achieved by depositing a thin layer of silicon germanium or germanium tin over suspended nanoribbons and then using an anneal process to drive the material throughout the nanoribbons, resulting in nanoribbons with a changing material composition along their lengths.

  • The nanoribbons have a changing material composition along their lengths, with regions at each end having no germanium and a region in between with a uniform non-zero germanium concentration.
  • This change in material composition imparts a compressive strain on the nanoribbons, which can enhance their performance in semiconductor devices.

Potential Applications

  • This technology can be used in the fabrication of high-performance semiconductor devices, such as transistors and sensors.
  • The increased strain in the nanoribbons can improve the electrical properties and overall performance of these devices.

Problems Solved

  • Traditional semiconductor devices may have limitations in terms of performance and efficiency.
  • By introducing a changing material composition and strain in the nanoribbons, this technology addresses these limitations and improves the performance of semiconductor devices.

Benefits

  • The increased strain in the nanoribbons can enhance the electrical properties of semiconductor devices, leading to improved performance.
  • This technique allows for the precise control of material composition and strain in nanoribbons, enabling the customization of semiconductor devices for specific applications.
  • The use of silicon germanium or germanium tin in the nanoribbons provides additional flexibility and options for semiconductor device design.


Original Abstract Submitted

Techniques are provided herein to form semiconductor devices having nanowires with an increased strain. A thin layer of silicon germanium or germanium tin can be deposited over one or more suspended nanoribbons. An anneal process may then be used to drive the silicon germanium or germanium tin throughout the one or more semiconductor nanoribbons, thus forming one or more nanoribbons with a changing material composition along the lengths of the one or more nanoribbons. In some examples, at least one of the one or more nanoribbons includes a first region at one end of the nanoribbon having substantially no germanium, a second region at the other end of the nanoribbon having substantially no germanium, and a third region between the first and second regions having a substantially uniform non-zero germanium concentration. The change in material composition along the length of the nanoribbon imparts a compressive strain.

Retrieved from "http://wikipatents.org/index.php?title=17523711._CLADDING_AND_CONDENSATION_FOR_STRAINED_SEMICONDUCTOR_NANORIBBONS_simplified_abstract_(Intel_Corporation)&oldid=22857"