17523086. MASKLESS ALIGNMENT SCHEME FOR BEOL MEMORY ARRAY MANUFACTURING simplified abstract (International Business Machines Corporation)
Contents
MASKLESS ALIGNMENT SCHEME FOR BEOL MEMORY ARRAY MANUFACTURING
Organization Name
International Business Machines Corporation
Inventor(s)
Soon-Cheon Seo of Glenmont NY (US)
Muthumanickam Sankarapandian of Niskayuna NY (US)
Raghuveer Reddy Patlolla of Guilderland NY (US)
MASKLESS ALIGNMENT SCHEME FOR BEOL MEMORY ARRAY MANUFACTURING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17523086 titled 'MASKLESS ALIGNMENT SCHEME FOR BEOL MEMORY ARRAY MANUFACTURING
Simplified Explanation
The patent application describes a method of manufacturing a semiconducting device using a semiconductor wafer. The process involves creating two different types of openings in the wafer, one for forming a bottom electrode hole and another for overlay/alignment purposes.
- The first opening is formed in a specific area of the wafer to create a bottom electrode hole.
- A deeper second opening is created in a different area of the wafer for overlay/alignment purposes.
- A bottom electrode metal layer is deposited, filling the first opening to form a bottom electrode and partially filling the second opening.
- A sacrificial material layer is then deposited above the bottom electrode layer, completely filling the second opening.
- A chemical-mechanical planarization process is performed to remove the bottom electrode metal and sacrificial layer, leaving a surface defined atop the remaining portion above the second opening.
- The sacrificial material layer is removed from the remaining portion of the second opening, leaving an overlay/alignment feature topography detectable for alignment and overlay measurement.
Potential applications of this technology:
- Semiconductor manufacturing
- Electronics industry
Problems solved by this technology:
- Improved alignment and overlay measurement in semiconductor manufacturing processes
Benefits of this technology:
- Enhanced accuracy in alignment and overlay measurement
- Simplified manufacturing process for semiconducting devices
Original Abstract Submitted
A method of manufacturing a semiconducting device that includes forming first opening for forming bottom electrode hole in a first area of a semiconductor wafer; forming a deeper second opening for overlay/alignment hole in second area; depositing a bottom electrode metal layer filling the first opening to form a bottom electrode and partially filling the second opening. A layer of sacrificial material is then deposited above the bottom electrode layer and completely filling the second opening. A chemical-mechanical planarization process is performed to remove the -bottom electrode metal and -sacrificial layer, the -sacrificial material layer being removed above a surface defined atop the filled remaining portion above the second opening. The sacrificial layer material is removed in the remaining portion of the second opening. The second opening providing an overlay/alignment feature topography detectable for alignment by lithography and for overlay measurement on the overlay metrology tool.
