17522974. GATE-CUT AND SEPARATION TECHNIQUES FOR ENABLING INDEPENDENT GATE CONTROL OF STACKED TRANSISTORS simplified abstract (International Business Machines Corporation)

GATE-CUT AND SEPARATION TECHNIQUES FOR ENABLING INDEPENDENT GATE CONTROL OF STACKED TRANSISTORS

Organization Name

International Business Machines Corporation

Inventor(s)

Ruilong Xie of Niskayuna NY (US)

Nicolas Loubet of GUILDERLAND NY (US)

Julien Frougier of Albany NY (US)

Lawrence A. Clevenger of Saratoga Springs NY (US)

PRASAD Bhosale of Albany NY (US)

Junli Wang of Slingerlands NY (US)

Balasubramanian Pranatharthiharan of Santa Clara CA (US)

Dechao Guo of Niskayuna NY (US)

GATE-CUT AND SEPARATION TECHNIQUES FOR ENABLING INDEPENDENT GATE CONTROL OF STACKED TRANSISTORS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17522974 titled 'GATE-CUT AND SEPARATION TECHNIQUES FOR ENABLING INDEPENDENT GATE CONTROL OF STACKED TRANSISTORS

Simplified Explanation

The abstract describes a patent application for vertically stacked field-effect transistors (FETs). These FETs consist of multiple transistors separated by a dielectric isolation layer. The transistors are surrounded by gate material and vertical layers of different heights.

• The invention is about vertically stacked field-effect transistors (FETs).
• The FETs include at least one first transistor and at least one second transistor.
• The transistors are separated by a dielectric isolation layer.
• The gate material is adjacent to both the first and second transistors.
• There is at least one first height vertical layer surrounding the gate material.
• There is also at least one second height vertical layer, which is shorter than the gate material.

Potential applications of this technology:

• Integrated circuits
• Microprocessors
• Memory devices
• Power amplifiers
• Communication devices

Problems solved by this technology:

• Increased performance and functionality of electronic devices
• Improved power efficiency
• Reduction in size and footprint of electronic components
• Enhanced integration of multiple transistors in a compact design

Benefits of this technology:

• Higher speed and processing capabilities
• Lower power consumption
• Smaller form factor
• Improved reliability and stability of electronic devices

Original Abstract Submitted

Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.