17522015. BOTTOM CONTACT FOR STACKED GAA FET simplified abstract (International Business Machines Corporation)
Contents
BOTTOM CONTACT FOR STACKED GAA FET
Organization Name
International Business Machines Corporation
Inventor(s)
Indira Seshadri of Niskayuna NY (US)
BOTTOM CONTACT FOR STACKED GAA FET - A simplified explanation of the abstract
This abstract first appeared for US patent application 17522015 titled 'BOTTOM CONTACT FOR STACKED GAA FET
Simplified Explanation
The abstract describes a method for constructing a semiconductor device. Here are the key points:
- The method involves forming a plurality of fins over a nanosheet stack and a substrate.
- Spacers are formed between the nanosheet stack and some of the fins, with each spacer having a different shape.
- Gate spacers are formed adjacent to the fins, directly contacting the fins with spacers.
- A barrier spacer is formed between a set of fins, directly contacting the top surface of a shallow trench isolation (STI) region.
- N-type epitaxial regions are formed between the fins.
- P-type epitaxy regions are formed over the n-type epitaxial regions.
- A first contact is formed vertically through the semiconductor device, adjacent to the barrier spacer, and extends laterally to directly contact the sidewall of an n-type epitaxial region.
Potential applications of this technology:
- Semiconductor devices used in electronic devices such as smartphones, computers, and tablets.
- Integrated circuits for various applications including data processing, communication, and control systems.
- Power electronics for efficient energy conversion and management.
- Sensor devices for detecting and measuring physical or chemical properties.
Problems solved by this technology:
- Enables the construction of semiconductor devices with improved performance and functionality.
- Provides a method for integrating different types of epitaxial regions and spacers in a semiconductor device.
- Enhances the contact between different regions of the device, improving overall device performance.
Benefits of this technology:
- Improved performance and functionality of semiconductor devices.
- Enhanced integration capabilities, allowing for more complex and advanced circuit designs.
- Better contact between different regions, leading to improved electrical conductivity and efficiency.
- Enables the development of smaller and more compact devices with higher performance.
Original Abstract Submitted
A method is presented for constructing a semiconductor device. The method includes forming a plurality of fins over a nanosheet stack and a substrate, forming spacers between the nanosheet stack and one or more of the plurality of fins, each spacer defining a different shape, forming gate spacers adjacent the plurality of fins, the gate spacers directly contacting the one or more of the plurality of fins having a spacer, forming a barrier spacer between a set of fins of the plurality of fins, the barrier spacer directly contacting a top surface of a shallow trench isolation (STI) region, forming n-type epitaxial regions between the plurality of fins, forming p-type epitaxy regions over the n-type epitaxial regions, and forming a first contact extending vertically through the semiconductor device adjacent the barrier spacer and extending laterally away from the barrier spacer to directly contact a sidewall of an n-type epitaxial region.
