17520812. Area Scaling for VTFET Contacts simplified abstract (International Business Machines Corporation)
Contents
Area Scaling for VTFET Contacts
Organization Name
International Business Machines Corporation
Inventor(s)
Yann Mignot of Slingerlands NY (US)
Lijuan Zou of Slingerlands NY (US)
Area Scaling for VTFET Contacts - A simplified explanation of the abstract
This abstract first appeared for US patent application 17520812 titled 'Area Scaling for VTFET Contacts
Simplified Explanation
The abstract describes techniques for area scaling of contacts in VTFET (Vertical Tunneling Field Effect Transistor) devices. These devices include a fin structure, bottom source/drain region, gate stack, top source/drain region, bottom source/drain contact, and gate contact. The bottom source/drain and gate contacts have a top portion with a width W and a bottom portion with a width Wover, where W<W. The sidewall along the top portion is discontinuous with the sidewall along the bottom portion. The bottom portion with the width Wis present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.
- VTFET devices with area scaling of contacts
- Contacts with a top portion and a bottom portion of different widths
- Discontinuous sidewall between the top and bottom portions
- Bottom portion present alongside the gate stack and top source/drain region
- Method for forming VTFET devices
Potential Applications
- Integrated circuits
- High-performance computing
- Power electronics
- Telecommunications
Problems Solved
- Area scaling of contacts in VTFET devices
- Improving device performance and efficiency
- Enhancing integration density in integrated circuits
Benefits
- Increased device performance and efficiency
- Improved integration density
- Enhanced functionality in various applications
- Potential for smaller and more compact devices
Original Abstract Submitted
Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width Wover a bottom portion having a width W, wherein W<W, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width Wis present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.
