17520672. ETCHING OF MAGNETIC TUNNEL JUNCTION (MTJ) STACK FOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) simplified abstract (International Business Machines Corporation)

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ETCHING OF MAGNETIC TUNNEL JUNCTION (MTJ) STACK FOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM)

Organization Name

International Business Machines Corporation

Inventor(s)

Koichi Motoyama of Clifton Park NY (US)

Oscar Van Der Straten of Guilderland Center NY (US)

Joseph F. Maniscalco of Greenville SC (US)

Chih-Chao Yang of Glenmont NY (US)

ETCHING OF MAGNETIC TUNNEL JUNCTION (MTJ) STACK FOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) - A simplified explanation of the abstract

This abstract first appeared for US patent application 17520672 titled 'ETCHING OF MAGNETIC TUNNEL JUNCTION (MTJ) STACK FOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM)

Simplified Explanation

The abstract describes a method for fabricating a semiconductor device and the resulting structure. Here are the key points:

  • The method involves forming a first set of spacers on the sidewalls of a bottom electrode.
  • A reference layer is then formed on the spacers and the bottom electrode.
  • A second set of spacers is formed on the sidewalls of the first set of spacers and the reference layer.
  • A tunnel barrier is formed on the reference layer and the second set of spacers.
  • A free layer is formed on the tunnel barrier, with a wider width than the reference layer.
  • A metal hardmask is formed on the free layer.
  • A third set of spacers is formed on the sidewalls of the metal hardmask, the free layer, the tunnel barrier, and the second set of spacers.

Potential applications of this technology:

  • Semiconductor devices such as magnetic tunnel junctions (MTJs) used in various electronic devices.
  • Memory devices, sensors, and logic circuits that require high-performance and low-power consumption.

Problems solved by this technology:

  • Provides a method for fabricating semiconductor devices with improved performance and reliability.
  • Enables the formation of complex structures with precise dimensions and control over material properties.

Benefits of this technology:

  • Improved performance and reliability of semiconductor devices.
  • Enhanced control over the dimensions and material properties of the fabricated structures.
  • Enables the development of advanced electronic devices with higher efficiency and functionality.


Original Abstract Submitted

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first set of spacers are formed on the sidewalls of a bottom electrode. A reference layer is formed on the spacers and the bottom electrode. A second set of spacers are formed on the sidewalls of the first set of spacers and the reference layer. A tunnel barrier is formed on the reference layer and the second set of spacers. A free layer is formed on the tunnel barrier, where a width of the free layer is greater than a width of the reference layer. A metal hardmask is formed on the free layer. A third set of spacers are formed on the sidewalls of the metal hardmask, the free layer, the tunnel barrier, and the second set of spacers.

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