17485005. Robust Transistor Circuitry simplified abstract (QUALCOMM Incorporated)
Contents
Robust Transistor Circuitry
Organization Name
Inventor(s)
Yi-Hung Tseng of San Diego CA (US)
Marzio Pedrali-noy of San Diego CA (US)
Charles James Persico of Rancho Santa Fe CA (US)
Robust Transistor Circuitry - A simplified explanation of the abstract
This abstract first appeared for US patent application 17485005 titled 'Robust Transistor Circuitry
Simplified Explanation
The patent application describes an apparatus for robust transistor circuitry, specifically a current mirror and fault handler circuitry. The current mirror consists of a core transistor, a first transistor, and a second transistor, all of which are connected to a control terminal. The fault handler circuitry is responsible for selecting either the first or second transistor to provide a mirrored current.
- The apparatus includes a current mirror and fault handler circuitry.
- The current mirror comprises a core transistor, a first transistor, and a second transistor.
- The control terminal of the first and second transistors is connected to the control terminal of the core transistor.
- The fault handler circuitry is designed to choose either the first or second transistor to generate a mirrored current.
Potential applications of this technology:
- Integrated circuits and semiconductor devices
- Robust transistor circuitry in electronic devices
- Power management systems
- Signal amplification and processing
Problems solved by this technology:
- Ensures robustness and reliability of transistor circuitry
- Provides fault handling capabilities for current mirrors
- Improves the performance and efficiency of integrated circuits
Benefits of this technology:
- Increases the stability and accuracy of current mirrors
- Enhances the overall performance of transistor circuitry
- Reduces the risk of failures and malfunctions in electronic devices
- Enables more efficient power management and signal processing.
Original Abstract Submitted
An apparatus is disclosed for robust transistor circuitry. In example implementations, an apparatus includes a current mirror and fault handler circuitry that is coupled to the current mirror. The current mirror includes a core transistor having a control terminal, a first transistor, and a second transistor. The first transistor has a control terminal that is coupled to the control terminal of the core transistor. The second transistor has a control terminal that is coupled to the control terminal of the core transistor. The fault handler circuitry is configured to select the first transistor or the second transistor to provide a mirrored current of the current mirror.
