17463370. FIELD EFFECT TRANSISTOR WITH FIN ISOLATION STRUCTURE AND METHOD simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
FIELD EFFECT TRANSISTOR WITH FIN ISOLATION STRUCTURE AND METHOD
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Kuo-Cheng Chiang of Hsinchu (TW)
FIELD EFFECT TRANSISTOR WITH FIN ISOLATION STRUCTURE AND METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 17463370 titled 'FIELD EFFECT TRANSISTOR WITH FIN ISOLATION STRUCTURE AND METHOD
Simplified Explanation
The abstract describes a device that includes a substrate and a fin isolation structure between two gate structures. The gate structures wrap around vertical stacks of nanostructure channels overlying fins. A trench isolation structure is present between the fin and the fin isolation structure, with different etch selectivity.
- The device includes a substrate and gate structures that wrap around vertical stacks of nanostructure channels overlying fins.
- A fin isolation structure is present between the gate structures, extending from the upper surface of the first gate structure to the upper surface of the substrate.
- A trench isolation structure is located between the fin and the fin isolation structure, with different etch selectivity.
Potential Applications
- This technology can be applied in the field of semiconductor devices and integrated circuits.
- It can be used in the manufacturing of high-performance transistors and other electronic components.
Problems Solved
- The device addresses the need for effective isolation between different gate structures and fins.
- It solves the problem of etch selectivity by providing a trench isolation structure with different properties.
Benefits
- The device provides improved isolation between gate structures, allowing for better control and performance of the electronic components.
- The use of different etch selectivity in the trench isolation structure enhances the manufacturing process and overall device performance.
Original Abstract Submitted
A device includes a substrate and a fin isolation structure between a first gate structure and a second gate structure. The first gate structure wraps around a first vertical stack of nanostructure channels overlying a first fin. The second gate structure wraps around a second vertical stack of nanostructure channels overlying a second fin. The fin isolation structure extends from an upper surface of the first gate structure to an upper surface of the substrate. A trench isolation structure is between the first fin and the fin isolation structure, and has different etch selectivity than the fin isolation structure.
