17462709. Integrated Circuit Structure with a Reduced Amount of Defects and Methods for Fabricating the Same simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

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Integrated Circuit Structure with a Reduced Amount of Defects and Methods for Fabricating the Same

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Chia-Hao Pao of Hsinchu (TW)

Chih-Hsuan Chen of Hsinchu (TW)

Chih-Chuan Yang of Hsinchu (TW)

Shih-Hao Lin of Hsinchu (TW)

Integrated Circuit Structure with a Reduced Amount of Defects and Methods for Fabricating the Same - A simplified explanation of the abstract

This abstract first appeared for US patent application 17462709 titled 'Integrated Circuit Structure with a Reduced Amount of Defects and Methods for Fabricating the Same

Simplified Explanation

The patent application describes a device that consists of two stacks of channel layers, each extending from a lower height to a higher height. There are two dielectric features on opposite sides of the first stack, extending from the lower height to different higher heights. A gate electrode spans across the top surface of both stacks, reaching a higher height than the dielectric features.

  • The device includes two stacks of channel layers with different heights.
  • There are dielectric features on opposite sides of the first stack, extending to different heights.
  • A gate electrode spans across the top surface of both stacks, reaching a higher height than the dielectric features.

Potential Applications

  • Semiconductor devices
  • Integrated circuits
  • Transistors

Problems Solved

  • Efficient control of electrical current in semiconductor devices
  • Improved performance and functionality of integrated circuits

Benefits

  • Enhanced electrical control and performance
  • Increased functionality and versatility in semiconductor devices
  • Improved efficiency and reliability in integrated circuits


Original Abstract Submitted

A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.