17462458. CHIP PACKAGE STRUCTURE WITH MULTIPLE GAP-FILLING LAYERS AND FABRICATING METHOD THEREOF simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

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CHIP PACKAGE STRUCTURE WITH MULTIPLE GAP-FILLING LAYERS AND FABRICATING METHOD THEREOF

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Po-Chen Lai of Hsinchu county (TW)

Ming-Chih Yew of Hsinchu City (TW)

Po-Yao Lin of Zhudong Township (TW)

Chin-Hua Wang of New Taipei City (TW)

Shin-Puu Jeng of Hsinchu (TW)

CHIP PACKAGE STRUCTURE WITH MULTIPLE GAP-FILLING LAYERS AND FABRICATING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17462458 titled 'CHIP PACKAGE STRUCTURE WITH MULTIPLE GAP-FILLING LAYERS AND FABRICATING METHOD THEREOF

Simplified Explanation

The abstract describes a chip package structure that includes an interposer substrate with two separate die regions and a gap region. It also includes two semiconductor dies placed over the die regions. The structure further includes three gap-filling layers: two layers separated from each other and one layer between them. The Young's modulus (a measure of stiffness) of the third layer is lower than the Young's modulus of the first and second layers.

  • The chip package structure consists of an interposer substrate with separate die regions and a gap region.
  • Two semiconductor dies are placed over the die regions.
  • Three gap-filling layers are included: two layers separated from each other and one layer between them.
  • The Young's modulus of the third layer is lower than the Young's modulus of the first and second layers.

Potential Applications

  • This chip package structure can be used in various electronic devices that require efficient and reliable chip packaging.
  • It can be applied in the manufacturing of microprocessors, memory chips, and other semiconductor devices.

Problems Solved

  • The chip package structure solves the problem of efficiently filling the gap region between die regions in a chip package.
  • It addresses the need for a structure that can provide appropriate stiffness and flexibility to accommodate different components and prevent damage.

Benefits

  • The use of multiple gap-filling layers with different Young's moduli allows for better stress distribution and protection of the chip package.
  • The structure provides improved reliability and performance by reducing the risk of damage to the semiconductor dies.
  • It offers flexibility in design and manufacturing processes, allowing for customization based on specific requirements.


Original Abstract Submitted

Structures and formation methods of a chip package structure are provided. The chip package structure includes an interposer substrate including first and second die regions that are separated by a gap region. The chip package structure also includes first and second semiconductor dies respectively arranged over the first and second die regions. In addition, the chip package structure includes first and second gap-filling layers formed over the gap region and separated from one another, and a third gap-filling layer over the gap region and between the first and second gap-filling layers. The Young's modulus of the third gap-filling layer is less than the Young's modulus of the first gap-filling layer and the Young's modulus of the second gap-filling layer.

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