17460764. Forming Interconnect Structures in Semiconductor Devices simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
Forming Interconnect Structures in Semiconductor Devices
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Hsiu-Wen Hsueh of Taichung City (TW)
Chii-Ping Chen of Hsinchu City (TW)
Chien-Chih Chiu of Tainan County (TW)
Forming Interconnect Structures in Semiconductor Devices - A simplified explanation of the abstract
This abstract first appeared for US patent application 17460764 titled 'Forming Interconnect Structures in Semiconductor Devices
Simplified Explanation
The patent application describes a method for forming conductive features on a substrate using an etch-stop layer (ESL) stack and interlayer dielectric (ILD) layers. Here are the key points:
- The method begins by forming a first conductive feature on a substrate.
- An etch-stop layer (ESL) stack is then formed over the first conductive feature.
- A first interlayer dielectric (ILD) layer is formed over the ESL stack.
- A patterned ESL with a first opening is formed over the first ILD layer.
- A second ILD layer is formed over the patterned ESL, filling the first opening.
- A patterned hard mask (HM) with a second opening, wider than the first opening, is formed over the second ILD layer.
- An etching process is performed to create a first trench in the second ILD layer and a second trench in the first ILD layer, exposing the first conductive feature.
- A conductive layer is then deposited in the first and second trenches, forming a second conductive feature that connects a third conductive feature to the first conductive feature.
Potential applications of this technology:
- Integrated circuit manufacturing
- Semiconductor device fabrication
- Electronics manufacturing
Problems solved by this technology:
- Provides a method for forming conductive features on a substrate with precise dimensions and interconnections
- Allows for the creation of complex circuitry and interconnects in a reliable and efficient manner
Benefits of this technology:
- Enables the production of high-performance integrated circuits and semiconductor devices
- Improves the reliability and functionality of electronic devices
- Reduces manufacturing costs and increases production efficiency
Original Abstract Submitted
A method includes forming a first conductive feature over a substrate, forming an etch-stop layer (ESL) stack over the first conductive feature, forming a first interlayer dielectric (ILD) layer over the ESL stack, forming a patterned ESL having a first opening over the first ILD layer, forming a second ILD layer over the patterned ESL, thereby filling the first opening, forming a patterned HM having a second opening over the second ILD layer, where a width of the second opening is greater than a width of the first opening, performing an etching process to form a first trench in the second ILD layer and a second trench in the first ILD layer, where the second trench exposes the first conductive feature, and subsequently depositing a conductive layer in the first trench and the second trench, thereby forming a second conductive feature interconnecting a third conductive to the first conductive feature.
