17460324. MEMORY ARRAY, INTEGRATED CIRCUIT INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

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MEMORY ARRAY, INTEGRATED CIRCUIT INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Wei-Sheng Yun of Taipei City (TW)

MEMORY ARRAY, INTEGRATED CIRCUIT INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract

This abstract first appeared for US patent application 17460324 titled 'MEMORY ARRAY, INTEGRATED CIRCUIT INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF

Simplified Explanation

The abstract describes a memory array structure in a patent application. Here is a simplified explanation of the abstract:

  • The memory array includes a first bit-line stack, a first spacer, a first data storage structure, and a word line.
  • The first bit-line stack consists of a first bit line and a first hard mask layer partially covering the top surface of the first bit line.
  • The first spacer is located on the lower sidewall of a first sidewall of the first bit line, exposing a top corner of the first bit line.
  • The first data storage structure covers the exposed top corner of the first bit line.
  • The word line covers a sidewall of the first data storage structure.

Potential applications of this technology:

  • Memory arrays in electronic devices such as computers, smartphones, and tablets.
  • Storage devices used in data centers and servers.

Problems solved by this technology:

  • Improved memory array structure that enhances data storage and retrieval.
  • More efficient use of space in memory arrays.

Benefits of this technology:

  • Increased memory capacity and performance.
  • Enhanced reliability and durability of memory arrays.
  • Cost-effective manufacturing process for memory arrays.


Original Abstract Submitted

A memory array includes a first bit-line stack disposed over a substrate, a first spacer, a first data storage structure, and a word line. The first bit-line stack includes a first bit line disposed over the substrate; and a first hard mask layer partially covering a top surface of the first bit line. The first spacer is disposed on a lower sidewall of a first sidewall of the first bit line. The first hard mask layer and the first spacer expose a top corner of the first bit line. The first data storage structure covers the top corner of the first bit line. The word line covers a sidewall of the first data storage structure.

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