17459379. SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Lung-Kun Chu of New Taipei (TW)
Kuan-Lun Cheng of Hsinchu (TW)
Kuo-Cheng Chiang of Hsinchu (TW)
SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17459379 titled 'SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
Simplified Explanation
The patent application describes a semiconductor device structure and methods of forming it. The structure includes dielectric features, a semiconductor layer, an isolation layer, a gate dielectric layer, and a gate electrode layer.
- The structure includes first and second dielectric features and a first semiconductor layer between them.
- An isolation layer is in contact with the first and second dielectric features.
- The first semiconductor layer is disposed over the isolation layer.
- A gate dielectric layer is disposed over the isolation layer.
- A gate electrode layer is disposed over the gate dielectric layer.
- The gate electrode layer extends to a level between the first and second surfaces of the first semiconductor layer.
Potential applications of this technology:
- Semiconductor devices such as transistors and integrated circuits.
- Electronics industry for various electronic devices.
Problems solved by this technology:
- Provides a structure for efficient and reliable semiconductor devices.
- Helps in improving the performance and functionality of electronic devices.
Benefits of this technology:
- Enhanced performance and functionality of semiconductor devices.
- Improved reliability and efficiency.
- Enables miniaturization and integration of electronic components.
Original Abstract Submitted
A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second dielectric features and a first semiconductor layer disposed between the first and second dielectric features. The structure further includes an isolation layer disposed between the first and second dielectric features, and the isolation layer is in contact with the first and second dielectric features. The first semiconductor layer is disposed over the isolation layer. The structure further includes a gate dielectric layer disposed over the isolation layer and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer has an end extending to a level between a first plane defined by a first surface of the first semiconductor layer and a second plane defined by a second surface opposite the first surface.
