17458730. SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Kuo-Cheng Chiang of Hsinchu (TW)
Jung-Chien Cheng of Hsinchu (TW)
Kuan-Lun Cheng of Hsinchu (TW)
SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17458730 titled 'SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME
Simplified Explanation
The patent application describes a semiconductor device structure and methods of forming it. The structure includes a dielectric feature with two layers, where the second layer is in contact with portions of the first layer. It also includes a semiconductor layer adjacent to one side of the first layer, and a gate electrode layer surrounding the semiconductor layer on three sides.
- The structure includes a dielectric feature with two layers.
- The second dielectric layer is in contact with portions of the first dielectric layer.
- A semiconductor layer is adjacent to one side of the first dielectric layer.
- A gate electrode layer surrounds the semiconductor layer on three sides.
Potential applications of this technology:
- Integrated circuits
- Transistors
- Semiconductor devices
Problems solved by this technology:
- Improved performance and functionality of semiconductor devices
- Enhanced control of electrical currents in the device
- Reduction of leakage currents
Benefits of this technology:
- Increased efficiency and reliability of semiconductor devices
- Enhanced integration and miniaturization capabilities
- Improved overall performance of electronic systems.
Original Abstract Submitted
A semiconductor device structure, along with methods of forming such, are described. The structure includes a dielectric feature comprising a first dielectric layer and a second dielectric layer, the first dielectric layer has a first sidewall and a second sidewall opposing the first sidewall, and the second dielectric layer is in contact with at least a portion of the first sidewall and at least a portion of the second sidewall. The structure also includes a first semiconductor layer adjacent the first sidewall, wherein the first semiconductor layer is in contact with the second dielectric layer. The structure further includes a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, wherein the first gate electrode layer has a surface facing the second dielectric layer, and the surface extends over a plane defined by an interface between the second dielectric layer and the first semiconductor layer.
